SEMICONDUCTOR MEMORY DEVICE

• US 20190198507A1
• Filed: 11/01/2018
• Published: 06/27/2019
• Est. Priority Date: 12/21/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NII, Koji, YABUUCHI, Makoto
• Granted Patent: US 10,644,009 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells; and

a word line coupled to the plurality of memory cells,

wherein the word line is extended in a first direction, and

wherein each of the plurality of memory cells includes a gate electrode extended along a second direction intersecting with the first direction.

2. The semiconductor memory device according to claim 1, further including a plurality of bit lines coupled to the memory cells,

wherein the bit lines are extended in the second direction.

3. The semiconductor memory device according to claim 2,

wherein the gate electrodes include a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided to be separated from each other and formed in a bending-free linear form,

wherein the first gate electrode and the third gate electrode are arranged to run in parallel in the first direction,

wherein the first gate electrode and the fourth gate electrode are linearly arranged in the second direction, and

wherein the third gate electrode and the second gate electrode are linearly arranged in the second direction.

4. The semiconductor memory device according to claim 3,

wherein each of the memory cells has a rectangular-shaped pattern slender in the second direction, and

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are arranged in the slender rectangular-shaped pattern.

5. The semiconductor memory device according to claim 4, wherein each of the memory cells is a static type memory cell including six MOS transistors.

6. The semiconductor memory device according to claim 2, wherein in each of the memory cells, the length of the word line corresponding to one memory cell is shorter than the length of the bit line corresponding to one memory cell.

7. A semiconductor memory device comprising:

a plurality of memory cells;

a word line coupled to the memory cells; and

a plurality of bit lines coupled to the memory cells,

wherein the word line is arranged to extend in a first direction,

wherein the plurality of bit lines are arranged to extend in a second direction intersecting with the first direction,

wherein each of the memory cells includes a plurality of gate electrodes extended in the second direction,

wherein each of the memory cells includes six MOS transistors, and

wherein the two of the six MOS transistors are arranged next to each other in the first direction.

8. The semiconductor memory device according to claim 7,

wherein the memory cells are extended in the first direction, and

wherein in the memory cells extended in the first direction, the two memory cells arranged next to each other share one of the bit lines.

9. The semiconductor memory device according to claim 7,

wherein the gate electrodes include a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided to be separated from each other and formed in a bending-free linear form,

wherein the first gate electrode and the third gate electrode are arranged to vertically run in parallel in the first direction,

wherein the first gate electrode and the fourth gate electrode are linearly arranged in the second direction, and

wherein the third gate electrode and the second gate electrode are linearly arranged in the second direction.

10. The semiconductor memory device according to claim 9,

wherein the six MOS transistors include first and second P channel MOS transistors, and first, second, third and fourth N channel MOS transistors,

wherein the first gate electrode is configured to be a gate of the first N channel MOS transistor,

wherein the second gate electrode is configured to be a gate of the second N channel MOS transistor,

wherein the third gate electrode is configured to be a gate of the first P channel MOS transistor and a gate of the third N channel MOS transistor, and

wherein the fourth gate electrode is configured to be a gate of the second P channel MOS transistor and a gate of the fourth N channel MOS transistor.

11. The semiconductor memory device according to claim 10,

wherein sources or drains of the first N channel MOS transistor and the third N channel MOS transistor are comprised of an N-type impurity region formed in a first P-type well region provided along the first direction,

wherein sources or drains of the second N channel MOS transistor and the fourth N channel MOS transistor are comprised of an N-type impurity region formed in a second P-type well region provided along the first direction, and

wherein sources or drains of the first and second P channel MOS transistors are comprised of a P-type impurity region formed in an N-type well region provided along the first direction and provided to be interposed by the first and second P-type well regions.

12. The semiconductor memory device according to claim 7,

wherein the semiconductor memory device is formed using first, second, third and fourth layer metal wirings,

wherein the word line is formed by one of the third layer metal wiring and the fourth layer metal wiring, and

wherein the bit lines are respectively formed by the other of the third layer metal wiring and the fourth layer metal wiring.

13. The semiconductor memory device according to claim 7,

wherein the semiconductor memory device is formed using first, second and third layer metal wirings,

wherein the word line is formed by one of the second layer metal wiring and the third layer metal wiring, and

wherein the bit lines are formed by the other of the second layer metal wiring and the third layer metal wiring.

14. A semiconductor memory device comprising:

a first word line and a second word line provided along a first direction;

a first bit line, a second bit line, and a third bit line provided along a second direction intersecting with the first direction;

a first memory cell coupled to the first word line, the first bit line, and the second bit line; and

a second memory cell coupled to the second word line, the second bit line, and the third bit line,

wherein each of the first memory cell and the second memory cell has a gate electrode extended in the second direction.

15. The semiconductor memory device according to claim 14,

wherein the gate electrodes include a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode,

wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided to be separated from each other and formed in a bending-free linear form,

wherein the first gate electrode and the third gate electrode are arranged to vertically run in parallel in the first direction,

wherein the first gate electrode and the fourth gate electrode are linearly arranged in the second direction, and

wherein the third gate electrode and the second gate electrode are linearly arranged in the second direction.

16. The semiconductor memory device according to claim 15,

wherein each of the first memory cell and the second memory cell includes first and second P channel MOS transistors, and first, second, third and fourth N channel MOS transistors,

wherein the first gate electrode is configured to be a gate of the first N channel MOS transistor,

wherein the second gate electrode is configured to be a gate of the second N channel MOS transistor,

wherein the third gate electrode is configured to be a gate of the first P channel MOS transistor and a gate of the third N channel MOS transistor, and

wherein the fourth gate electrode is configured to be a gate of the second P channel MOS transistor and a gate of the fourth N channel MOS transistor.

17. The semiconductor memory device according to claim 16,

wherein sources or drains of the first N channel MOS transistor and the third N channel MOS transistor are comprised of an N-type impurity region formed in a first P-type well region provided along the first direction,

wherein sources or drains of the second N channel MOS transistor and the fourth N channel MOS transistor are comprised of an N-type impurity region formed in a second P-type well region provided along the first direction, and

wherein sources or drains of the first and second P channel MOS transistors are comprised of a P-type impurity region formed in an N-type well region provided along the first direction and provided to be interposed by the first and second P-type well regions.

18. The semiconductor memory device according to claim 17,

wherein the semiconductor memory device is formed using first, second, third and fourth layer metal wirings,

wherein the first and second word lines are respectively formed by one of the third layer metal wiring and the fourth layer metal wiring, and

wherein the first through third bit lines are respectively formed by the other of the third layer metal wiring and the fourth layer metal wiring.

19. The semiconductor memory device according to claim 17,

wherein the semiconductor memory device is formed using first, second and third layer metal wirings,

wherein the first and second word lines are respectively formed by one of the second layer metal wiring and the third layer metal wiring, and

wherein the first through third bit lines are respectively formed by the other of the second layer metal wiring and the third layer metal wiring.