System, Apparatus And Method For Controlling Allocations Into A Branch Prediction Circuit Of A Processor
First Claim
1. An apparatus comprising:
- a first local predictor circuit having a first plurality of entries each to store local prediction information for a corresponding branch instruction;
a global predictor circuit having a plurality of global entries each to store global prediction information for a corresponding branch instruction; and
a second local predictor circuit having a second plurality of entries each to store second local prediction information for a corresponding branch instruction, wherein an entry of the second local predictor circuit is to be updated in response to every execution of the corresponding branch instruction.
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Abstract
In one embodiment, a branch prediction circuit includes: a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction. Other embodiments are described and claimed.
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Citations
20 Claims
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1. An apparatus comprising:
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a first local predictor circuit having a first plurality of entries each to store local prediction information for a corresponding branch instruction; a global predictor circuit having a plurality of global entries each to store global prediction information for a corresponding branch instruction; and a second local predictor circuit having a second plurality of entries each to store second local prediction information for a corresponding branch instruction, wherein an entry of the second local predictor circuit is to be updated in response to every execution of the corresponding branch instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
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receiving, in a branch predictor of a processor, feedback information regarding execution of a branch instruction from an execution circuit of the processor; upon a determination that the feedback information indicates that an entry of a shadow bimodal predictor of the branch predictor correctly predicted the branch instruction, probabilistically updating a counter of an entry of a monitoring table of the branch predictor, the entry associated with the branch instruction; and allocating a new entry in a global predictor of the branch predictor in response to a misprediction regarding the branch instruction by a local predictor when the counter of the entry of the monitoring table is less than a threshold. - View Dependent Claims (13, 14, 15, 16)
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17. A processor comprising:
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a branch prediction circuit comprising; a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction; and an execution circuit to execute instructions, wherein the execution circuit is to provide feedback information regarding branch instructions to the branch prediction circuit. - View Dependent Claims (18, 19, 20)
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Specification