MEMORY SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCTS
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Abstract
In various embodiments, an apparatus is provided, comprising: a first semiconductor platform including a first memory; and a second semiconductor platform stacked with the first semiconductor platform and including a second memory; wherein the apparatus is operable for: receiving a read command or write command, identifying one or more faulty components of the apparatus, and adjusting at least one timing in connection with the read command or write command, in response to the identification of the one or more faulty components of the apparatus.
174 Citations
82 Claims
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1-20. -20. (canceled)
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21. An apparatus, comprising:
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a first semiconductor platform including a first memory; and a second semiconductor platform stacked with the first semiconductor platform and including a second memory; wherein the apparatus is operable for; receiving a read command or write command, identifying one or more faulty components of the apparatus, and adjusting at least one timing in connection with the read command or write command, in response to the identification of the one or more faulty components of the apparatus. - View Dependent Claims (22, 23, 24, 25, 26, 79, 80, 81)
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27. An apparatus, comprising:
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circuitry for use with; a first semiconductor platform including a first memory, and a second semiconductor platform stacked with the first semiconductor platform and including a second memory; wherein the apparatus is operable for; identifying one or more faulty components of at least one of the first semiconductor platform or the second semiconductor platform, and adjusting at least one aspect in connection with at least one command communicated via a bus operable for variable latency such that a first latency of a first response to a first command is capable of being different than a second latency of a second response to a second command, based on the identification of the one or more faulty components of at least one of the first semiconductor platform or the second semiconductor platform. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78)
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41. An apparatus, comprising:
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a first semiconductor platform including a first memory; and a second semiconductor platform stacked with the first semiconductor platform and including a second memory; means for; identifying one or more faulty components of the apparatus; and adjusting at least one aspect in connection with a read command or a write command, in response to the identification of the one or more faulty components of the apparatus.
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82. An apparatus, comprising:
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a first semiconductor platform including a first memory; a second semiconductor platform stacked with the first semiconductor platform and including a second memory; and circuitry in communication with the first memory and the second memory, the circuitry configured to; identify one or more faulty components of the apparatus, and adjust at least one aspect in connection with a read command or a write command, in response to the identification of the one or more faulty components of the apparatus.
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Specification