SEMICONDUCTOR DEVICES, AND RELATED CONTROL LOGIC ASSEMBLIES, ELECTRONIC SYSTEMS, AND METHODS

• US 20190206449A1
• Filed: 11/28/2018
• Published: 07/04/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beigel, Kurt D., Sills, Scott E.
• Granted Patent: US 10,672,432 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/10 : Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type

Abstract

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

Claims

1. A semiconductor device, comprising:

a stack structure comprising decks each comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.

2. The semiconductor device of claim 1, further comprising a base control logic structure in electrical communication with the stack structure and comprising additional control logic devices.

3. The semiconductor device of claim 2, wherein the additional control logic devices of the base control logic structure exhibit different configurations and have different operational functions than the control logic devices of the control logic level of each of the decks of the stack structure.

4. The semiconductor device of claim 2, wherein:

the control logic devices of the control logic level of each of the decks of the stack structure comprise one or more of local deck decoders, column decoders, row decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh devices; and

the additional control logic devices of the base control logic structure comprise one or more of charge pumps, delay-locked loop devices, and drain supply voltage regulators.

5. The semiconductor device of claim 1, wherein the memory element level further comprises access devices electrically connected to the memory elements.

6. The semiconductor device of claim 1, further comprising an access device level comprising access devices electrically connected to the memory elements of the memory element level, the control logic level in electrical communication with the access device level.

7. The semiconductor device of claim 1, wherein the control logic level of each of the decks of the stack structure exhibits substantially the same configuration as the control logic level of each other of the decks of the stack structure.

8. The semiconductor device of claim 1, wherein the at least one device comprises one or more of an inverter, a two-input NAND gate, a balanced inverter, a balanced transmission pass gate, and a balanced two-input NAND gate.

9. The semiconductor device of claim 1, wherein the gate electrode of the at least one device laterally intervenes between channel regions of the neighboring vertical transistors.

10. The semiconductor device of claim 1, wherein the at least one device comprises at least one circuit comprising at least one vertical transistor having an N-type channel region, and at least one additional vertical transistor having a P-type channel region, the at least one vertical transistor sharing at least one gate electrode thereof with the at least one additional vertical transistor.

11. A control logic assembly comprising control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices, at least one of the control logic devices comprising at least one device exhibiting one or more gate electrodes shared by neighboring vertical transistors thereof.

12. The control logic assembly of claim 11, wherein more than one of the control logic devices of the control logic assembly individually comprise the at least one device.

13. The control logic assembly of claim 11, wherein:

semiconductive structures of a pair of the vertical neighboring transistors of the at least one device are aligned with one another in a first lateral direction; and

a gate electrode shared by the pair of the neighboring vertical transistors laterally intervenes between the semiconductive structures of the pair of the neighboring vertical transistors in a second lateral direction substantially perpendicular to the first lateral direction.

14. The control logic assembly of claim 11, wherein the at least one device further exhibits one or more additional gate electrodes not shared by the neighboring vertical transistors thereof.

15. The control logic assembly of claim 11, wherein the at least one device exhibits a gate electrode shared by multiple pairs of neighboring vertical transistors thereof.

16. A method of forming a control logic device, comprising:

forming N-type line structures extending over a substrate in a first lateral direction;

forming P-type line structures extending over the substrate in the first lateral direction and intervening between the N-type line structures in a second lateral direction perpendicular to the first lateral direction;

removing portions of the N-type line structures and the P-type line structures to form first N-type pillar structures, first P-type pillar structures, and first linear trenches extending over the substrate in the second lateral direction;

forming first linear isolation structures within the first linear trenches;

removing portions of the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures to form second N-type pillar structures, second P-type pillar structures, first isolation structures, and second linear trenches extending over the substrate in the first lateral direction;

forming gate electrodes in the second linear trenches, some of the second linear trenches including only one of the gate electrodes and other of the second linear trenches including more than one of the gate electrodes; and

forming second linear isolation structures in portions of the second linear trenches remaining after forming the gate electrodes.

17. The method of claim 16, further comprising forming linear spacer structures over opposing sidewalls of each of the N-type line structures prior to forming the P-type line structures.

18. The method of claim 16, wherein removing portions of the N-type line structures and the P-type line structures comprises:

providing a mask structure over at least the N-type line structures and the P-type line structures, the mask structure comprising linear structures and linear apertures each extending in the second lateral direction; and

substantially removing regions of at least the N-type line structures and the P-type line structures underlying the linear apertures in the mask structure.

19. The method of claim 16, further comprising forming first linear dielectric liner structures intervening between the first linear isolation structures and surfaces of at least the first N-type pillar structures, the first P-type pillar structures, and the substrate within the first linear trenches.

20. The method of claim 16, wherein removing portions of the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures comprises:

providing a mask structure at least over the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures, the mask structure comprising linear structures and linear apertures each extending in the first lateral direction; and

substantially removing regions of at least the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures underlying the linear apertures in the mask structure.

21. The method of claim 16, wherein removing portions of the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures comprises forming some of the second linear trenches to be wider in the second lateral direction than some other of the second linear trenches.

22. The method of claim 21, wherein forming gate electrodes in the second linear trenches comprises forming two gate electrodes in each relatively wider second linear trench and only one gate electrode in each relatively narrower second linear trench.

23. The method of claim 16, further comprising forming a gate dielectric liner material within the second linear trenches prior to forming the gate electrodes within the second linear trenches.

24. A method of operating a semiconductor device, comprising:

controlling functions of a stack structure having multiple decks each comprising memory cells using control logic levels of the multiple decks, the control logic levels each comprising at least one control logic device exhibiting a gate electrode shared by neighboring vertical transistors thereof; and

controlling additional functions of the stack structure using a base control logic structure in electrical communication with the control logic levels of the stack structure.

25. An electronic system, comprising:

a semiconductor device comprising;

a stack structure comprising decks each comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.