SEMICONDUCTOR DEVICES, AND RELATED CONTROL LOGIC ASSEMBLIES, ELECTRONIC SYSTEMS, AND METHODS
First Claim
1. A semiconductor device, comprising:
- a stack structure comprising decks each comprising;
a memory element level comprising memory elements; and
a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.
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Accused Products
Abstract
A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.
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Citations
25 Claims
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1. A semiconductor device, comprising:
a stack structure comprising decks each comprising; a memory element level comprising memory elements; and a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- 11. A control logic assembly comprising control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices, at least one of the control logic devices comprising at least one device exhibiting one or more gate electrodes shared by neighboring vertical transistors thereof.
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16. A method of forming a control logic device, comprising:
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forming N-type line structures extending over a substrate in a first lateral direction; forming P-type line structures extending over the substrate in the first lateral direction and intervening between the N-type line structures in a second lateral direction perpendicular to the first lateral direction; removing portions of the N-type line structures and the P-type line structures to form first N-type pillar structures, first P-type pillar structures, and first linear trenches extending over the substrate in the second lateral direction; forming first linear isolation structures within the first linear trenches; removing portions of the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures to form second N-type pillar structures, second P-type pillar structures, first isolation structures, and second linear trenches extending over the substrate in the first lateral direction; forming gate electrodes in the second linear trenches, some of the second linear trenches including only one of the gate electrodes and other of the second linear trenches including more than one of the gate electrodes; and forming second linear isolation structures in portions of the second linear trenches remaining after forming the gate electrodes. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A method of operating a semiconductor device, comprising:
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controlling functions of a stack structure having multiple decks each comprising memory cells using control logic levels of the multiple decks, the control logic levels each comprising at least one control logic device exhibiting a gate electrode shared by neighboring vertical transistors thereof; and controlling additional functions of the stack structure using a base control logic structure in electrical communication with the control logic levels of the stack structure.
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25. An electronic system, comprising:
a semiconductor device comprising; a stack structure comprising decks each comprising; a memory element level comprising memory elements; and a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.
Specification