PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE

• US 20190206792A1
• Filed: 12/28/2017
• Published: 07/04/2019
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Collins, Andrew, Penmecha, Bharat P., Swaminathan, Rajasekaran, Viswanath, Ram
• Granted Patent: US 10,643,945 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/23 Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA

Abstract

Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

Claims

1. A semiconductor package comprising:

a first die comprising a first bridge interconnect region;

a second die comprising a second bridge interconnect region;

a bridge die comprising a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, wherein

the first bridge interconnect region is larger than the second bridge interconnect region;

each of the first bridge interconnect region and the second bridge interconnect region comprise a plurality of conductive bumps; and

an average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

2. The semiconductor package of claim 1, wherein at least one of the first die and the second die are independently chosen from a central processing unit, a flash memory, a Wi-Fi transmitter, and a global positioning system.

3. The semiconductor package of claim 1, wherein the average pitch between bumps of the first bridge interconnect region is in a range of from about 10 times to about 0.25 times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

4. The semiconductor package of claim 1, wherein the average pitch between bumps of the first bridge interconnect region is in a range of from about 75 microns to about 150 microns.

5. The semiconductor package of claim 1, wherein the average pitch between bumps of the second bridge interconnect region is in a range of from about 20 microns to about 70 microns.

6. The semiconductor package of claim 1, wherein the first die is larger by at least one of surface area and volume than the second die.

7. The semiconductor package of claim 1, wherein the second die further comprises a first breakout region comprising a plurality of conductive bumps located adjacent the second interconnect region at a first location.

8. The semiconductor package of claim 7, wherein a pitch between the adjacent bumps of at least one of the first breakout region and the second breakout region is in a range of from about 10 times to about 0.5 times larger than the pitch of adjacent bumps of the second interconnect region.

9. A semiconductor package comprising:

a first die comprising a first bridge interconnect region;

a second die comprising a second bridge interconnect region;

a bridge die comprising a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, wherein

the first bridge interconnect region is larger than the second bridge interconnect region;

the first die is larger by at least one of surface area and volume than the second die;

each of the first bridge interconnect region and the second bridge interconnect region comprise a plurality of conductive bumps; and

an average pitch between bumps of the first bridge interconnect region is in a range of from about 10 times to about 0.25 times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

10. The semiconductor package of claim 9, wherein the average pitch between bumps of the first bridge interconnect region is in a range of from about 2 times to about 0.5 times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

11. The semiconductor package of claim 9, wherein the conductive bumps of at least one of the first bridge interconnect region and the second bridge interconnect region comprise copper.

12. The semiconductor package of claim 9, wherein the first bridge interconnect region is in a range of from about 10 times to about 0.5 times larger than the second bridge interconnect region.

13. The semiconductor package of claim 9, wherein the first bridge interconnect region is in a range for from about 5 times to about 2 times larger than the second bridge interconnect region.

14. The semiconductor package of claim 9, wherein the second die further comprises a first breakout region comprising a plurality of conductive bumps located adjacent the second interconnect region at a first location.

15. The semiconductor package of claim 14, wherein the second die further comprises a second breakout region comprising the plurality of conductive bumps located adjacent the second interconnect region at a second location.

16. A method of making a semiconductor package, the method comprising:

connecting a first die to a bridge die along a first bridge interconnect region;

connecting a second die to the bridge die along a second bridge interconnect region;

wherein

the first bridge interconnect region is larger than the second bridge interconnect region;

each of the first bridge interconnect region and the second bridge interconnect region comprise a plurality of conductive bumps; and

an average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

17. The method of claim 16, further comprising at least partially embedding at least one of the first die, the second die, and the die in a substrate.

18. The semiconductor package of claim 16, wherein an average pitch between bumps of the first bridge interconnect region is in a range of from about 10 times to about 0.25 times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

19. The semiconductor package of claim 16, wherein the first die is larger by at least one of surface area and volume than the second die.

20. The semiconductor package of claim 16, further comprising a plurality of conductive bumps located on the bridge at a location between the first die and the second die.