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PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE

  • US 20190206792A1
  • Filed: 12/28/2017
  • Published: 07/04/2019
  • Est. Priority Date: 12/28/2017
  • Status: Active Grant
First Claim
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1. A semiconductor package comprising:

  • a first die comprising a first bridge interconnect region;

    a second die comprising a second bridge interconnect region;

    a bridge die comprising a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, whereinthe first bridge interconnect region is larger than the second bridge interconnect region;

    each of the first bridge interconnect region and the second bridge interconnect region comprise a plurality of conductive bumps; and

    an average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

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