SELF-ALIGNED AND MISALIGNMENT-TOLERANT LANDING PAD FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

• US 20190207099A1
• Filed: 12/28/2017
• Published: 07/04/2019
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: ANNUNZIATA, Anthony J., KOTHANDARAMAN, Chandrasekharan, MARCHACK, Nathan P., O'SULLIVAN, Eugene J.
• Granted Patent: US 10,644,232 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a pad layer on and in contact with at least one trench line formed within a substrate;

depositing magnetic tunnel junction stack layers on and in contact with the pad layer; and

etching the magnetic tunnel junction stack layers to form a magnetic tunnel junction stack, where the etching stops on the pad layer.

2. The method of claim 1, further comprising:

prior to forming the pad layer, forming a trench within a substrate;

forming a liner within the trench; and

forming the at least one trench line within the trench and in contact with the liner.

3. The method of claim 1, further comprising:

prior to depositing the magnetic tunnel junction stack layers, planarizing the pad layer.

4. The method of claim 1, wherein etching the magnetic tunnel junction stack layers to form a magnetic tunnel junction stack comprises:

forming a hardmask on the magnetic tunnel junction stack layers; and

etching portions of the magnetic tunnel junction stack layers not underlying the hardmask.

5. The method of claim 4, further comprising:

etching portions of the pad layer not underlying the hardmask and above the substrate.

6. The method of claim 5, wherein etching portions of the pad layer exposes at least a top surface of the substrate and a surface of the pad layer within a recessed area of the at least one trench line.

7. The method of claim 1, further comprising:

depositing a spacer material over and in contact with the pad layer, the magnetic tunnel junction stack, and the hardmask.

8. The method of claim 7, further comprising:

etching the spacer material to form a spacer on sidewalls of the magnetic tunnel junction stack, and the hardmask.

9. The method of claim 8, further comprising:

etching portions of the pad layer not underlying the spacer.

10. A semiconductor device comprising:

a substrate;

at least one trench line formed within the substrate;

a self-aligned landing pad in contact with the at least one trench line; and

a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad.

11. The semiconductor device of claim 10, further comprising:

a spacer formed on and in contact with at least the self-aligned landing pad.

12. The semiconductor device of claim 11, wherein the spacer is further formed on top of and in contact with the self-aligned landing pad.

13. The semiconductor device of claim 10, wherein the self-aligned landing pad comprises a first portion above a top surface of the substrate and a second portion that extends below the top surface of the substrate, wherein the first portion does not extend laterally beyond the magnetic tunnel junction stack, and wherein the second portion extends laterally beyond the magnetic tunnel junction stack.

14. The semiconductor device of claim 10, wherein the self-aligned landing pad comprises tantalum nitride.

15. The semiconductor device of claim 10, wherein the substrate further comprises a trench, wherein the trench comprises a liner, and wherein the at least one trench line contacts the liner.

16. An integrated circuit comprising:

at least one semiconductor device, wherein the at least one semiconductor device comprises

a substrate;

at least one trench line formed within the substrate;

a self-aligned landing pad in contact with the at least one trench line; and

a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad.

17. The integrated circuit of claim 16, wherein the at least one semiconductor device further comprises:

a spacer formed on and in contact with at least the self-aligned landing pad.

18. The integrated circuit of claim 17, wherein the spacer is further formed on top of and in contact with the self-aligned landing pad.

19. The integrated circuit of claim 16, wherein the self-aligned landing pad comprises a first portion above a top surface of the substrate and a second portion that extends below the top surface of the substrate, wherein the first portion does not extend laterally beyond the magnetic tunnel junction stack, and wherein the second portion extends laterally beyond the magnetic tunnel junction stack.

20. The integrated circuit of claim 16, wherein the self-aligned landing pad comprises tantalum nitride.