RF-DAC BASED PHASE MODULATOR

• US 20190207565A1
• Filed: 01/03/2018
• Published: 07/04/2019
• Est. Priority Date: 01/03/2018
• Status: Active Grant

• Current Assignee: Technische Universiteit Delft
• Original Assignee: Technische Universiteit Delft
• Inventors: de Vreede, Leonardus Cornelius Nicolaas, Alavi, Seyed Morteza, Mehrpoo, Mohammedreza, Polushkin, Mikhail Evgenyevich, Hashemi, Mohsen, Shen, Yiyu
• Granted Patent: US 10,644,656 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 1/3223 using feed-forward H03F1/3211 takes precedence
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03M 1/662 Multiplexed conversion systems
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

A wideband, frequency agile, radio frequency digital-to-analog converter (RF-DAC) based phase modulator includes first, second, and third RF-DACs, each configured to upconvert an input I/Q digital baseband signal pair to a local oscillator (LO) frequency but with the first RF-DAC being driven by a first set of LO clocks, the second RF-DAC being driven by a second set of LO clocks that is forty-five degrees out of phase with respect to the first set of LO clocks, and the third RF-DAC being driven by a third set of LO clocks that is a further forty-five degrees out of phase with respect to the second set of LO clocks. First, second, and third upconverted analog signals produced by the first, second, and third RF-DACs are combined to reinforce the fundamental LO component while canceling 3^rd-order and 5^th-order LO harmonics.

Claims

1. A radio frequency (RF) phase modulator, comprising:

a first RF digital-to-analog converter (RF-DAC) having a first pair of in-phase (I) and quadrature (Q) inputs configured to receive an I/Q digital baseband signal pair formatted according to a predetermined digital modulation scheme, a first plurality of local oscillator (LO) clock inputs configured to receive a first plurality of LO clock signals, and an RF output;

a second RF-DAC having a second pair of I and Q inputs configured to receive the I/Q digital baseband signal pair, a second plurality of LO clock inputs configured to receive a second plurality of LO clock signals of different phases relative to the first plurality of LO clock signals, and an RF output coupled to the RF output of the first RF-DAC; and

a third RF-DAC having a third pair of I and Q inputs configured to receive the I/Q digital baseband signal pair, a third plurality of LO clock inputs configured to receive a third plurality of LO clock signals of different phases relative to the second plurality of LO clock signals, and an RF output coupled to the RF outputs of the first and second RF-DACs.

2. The RF phase modulator of claim 1, wherein the second plurality of LO clock signals is phase shifted forty-five degrees with respect to the first plurality of LO clock signals and the third plurality of LO clock signals is phase shifted forty-five degrees with respect to the second plurality of LO clock signals.

3. The RF phase modulator of claim 1, wherein each of the first, second, and third RF-DACs comprises an I-path RF-DAC and a Q-path RF-DAC.

4. The RF phase modulator of claim 3, wherein the I-path RF-DAC comprises an I-path current steering DAC and the Q-path RF-DAC comprises a Q-path current steering DAC.

5. The RF phase modulator of claim 4, wherein the I-path current steering DAC is an I-path current steering RF-DAC, the Q-path current steering DAC is a Q-path current steering RF-DAC, and the I-path and Q-path current steering RF-DACs each includes a plurality of RF-DAC unit cells.

6. The RF phase modulator of claim 5, wherein each RF-DAC unit cell comprises mixing logic that upconverts an associated input digital bit stream to an LO frequency, a current source, and one or more switches that connect and disconnect the current source to and from a load in response to an upconverted bit stream produced by the mixing logic.

7. The RF phase modulator of claim 1, wherein each of the first, second, and third RF-DACs comprises an I-Q interleaving DAC.

8. The RF phase modulator of claim 7, wherein each I-Q interleaving DAC comprises a current steering DAC including a plurality of DAC unit cells.

9. The RF phase modulator of claim 8, wherein each I-Q interleaving DAC is an I-Q interleaving RF-DAC, each I-Q interleaving RF-DAC comprises a current steering RF-DAC, and each current steering RF-DAC comprises a plurality of RF-DAC unit cells.

10. The RF phase modulator of claim 9, wherein each RF-DAC unit cell comprises mixing logic that upconverts an input digital bit stream to an LO frequency, a current source, and one or more switches that connect and disconnect the current source to and from a load in response to an upconverted bit stream produced by the mixing logic.

11. The RF phase modulator of claim 1, further comprising a low-pass filter (LPF) coupled to the RF outputs of the first, second, and third RF-DACs.

12. The RF phase modulator of claim 11, further comprising a limiter coupled to an output of the LPF.

13. A harmonic rejection phase modulation method, comprising:

receiving an input in-phase (I)/quadrature (Q) digital baseband signal pair formatted according to a predetermined digital modulation scheme;

upconverting the input I/Q digital baseband signal pair to an LO frequency in accordance with a first set of LO clocks to produce a first upconverted I/Q digital signal;

converting the first upconverted I/Q signal to a first upconverted analog signal;

upconverting the input I/Q digital baseband signal pair to a LO frequency in accordance with a second set of LO clocks that is shifted in phase with respect to the first set of LO clocks to produce a second upconverted I/Q digital signal;

converting the second upconverted I/Q signal to a second upconverted analog signal;

upconverting the input I/Q digital baseband signal pair to a LO frequency in accordance with a third set of LO clocks that is shifted in phase with respect to the second set of LO clocks to produce a third upconverted I/Q digital signal;

converting the third upconverted I/Q signal to a third upconverted analog signal; and

combining the first, second, and third upconverted analog signals to produce a combined upconverted analog signal, said combining including constructively combining a fundamental LO component and destructively combining 3^rd-order and 5^th-order LO harmonics.

14. The method of claim 13, wherein the second set of LO clocks is phase shifted forty-five degrees with respect to the first set of LO clocks and the second set of LO clocks is phase shifted forty-five degrees with respect to the second set of LO clocks.

15. The method of claim 13, wherein:

upconverting the input I/Q digital baseband signal pair to the first upconverted I/Q digital signal and converting the first upconverted I/Q signal to the first upconverted analog signal is performed by a first radio frequency digital-to-analog converter (first RF-DAC);

upconverting the input I/Q digital baseband signal pair to the second upconverted I/Q digital signal and converting the second upconverted I/Q signal to the second upconverted analog signal is performed by a second radio frequency digital-to-analog converter (second RF-DAC); and

upconverting the input I/Q digital baseband signal pair to the third upconverted I/Q digital signal and converting the third upconverted I/Q signal to the third upconverted analog signal is performed by a third radio frequency digital-to-analog converter (third RF-DAC).

16. The method of claim 15, wherein the first, second, and third RF-DACs each comprises an I-path RF-DAC and Q-path RF-DAC.

17. The method of claim 16, wherein each I-path RF-DAC comprises an I-path current steering DAC and each Q-path RF-DAC comprises a Q-path current steering DAC.

18. The method of claim 17, wherein each of the I-path current steering DACs is an I-path current steering RF-DAC having a first plurality of RF-DAC unit cells and each of the Q-path current steering DACs is a Q-path current steering RF-DAC having a second plurality of RF-DAC unit cells.

19. The method of claim 18, wherein each of the RF-DACs in both the first an second pluralities of RF-DAC unit cells comprises mixing logic that upconverts an associated digital bit stream to the LO frequency, a current source, and one or more switches that connect and disconnect the current source to and from a load in response to an upconverted bit stream produced by the mixing logic.

20. The method of claim 15, wherein the first, second, and third upconverted I/Q digital signals are first, second, and third I-Q interleaved signals and each of the first, second, and third RF-DACs comprises an I-Q interleaving RF-DAC.

21. The method of claim 20, wherein each of the I-Q interleaving RF-DACs comprises a current steering DAC.

22. The method of claim 21, wherein each of the current steering DACs is a current steering RF-DAC having a plurality of RF-DAC units cells.

23. The method of claim 22, wherein each RF-DAC unit cell comprises mixing logic that upconverts an associated digital bit stream to the LO frequency, a current source, and one or more switches that connect and disconnect the current source to and from a load in response to an upconverted bit stream produced by the mixing logic.

24. A radio frequency (RF) transmitter, comprising:

a digital signal processor (DSP) configured to generate digital in-phase (I) and quadrature (Q) baseband signals;

an RF digital-to-analog converter (RF-DAC) based phase modulator configured to upconvert the digital I and Q baseband signals to a local oscillator (LO) frequency in accordance with a multi-phase set of LO clocks, convert the resulting digital upconverted I and Q signals to an analog phase-modulated drive signal, and suppress 3^rd-order and 5^th-order LO harmonics; and

a power amplifier (PA) configured to be driven by the analog phase-modulated drive signal.

25. The RF transmitter of claim 24, wherein the DSP is further configured to convert the digital I and Q baseband signals to a digital amplitude modulation (AM) signal, the PA comprises a digital power amplifier (DPA), and the RF transmitter further comprises an amplitude code word (ACW) generator that produces an ACW signal, in accordance with the AM represented in the digital AM signal, that affects and controls a signal envelope of a phase-modulated RF signal produced by the DPA.

26. The RF transmitter of claim 24, wherein the DSP is further configured to convert the digital I and Q baseband signals to a digital amplitude modulation (AM) signal, the PA comprises a switch-mode PA (SMPA), and the RF transmitter further comprises a dynamic power supply (DPS) configured to receive the digital AM signal and produce a DPS voltage V_DD(t) that affects and controls a signal envelope of a phase-modulated RF signal produced by the SMPA.

27. A digital Doherty power amplifier, comprising:

a main radio frequency digital-to-analog converter (RF-DAC) based phase modulator configured to upconvert main digital I and Q baseband signals to a local oscillator (LO) frequency in accordance with a first multi-phase set of LO clocks and convert the resulting digital upconverted main I and Q signals to a main analog phase-modulated drive signal;

a peaking RF-DAC phase modulator configured to upconvert the peaking digital I and Q baseband signals to an LO frequency in accordance with a second multi-phase set of LO clocks and convert the resulting digital upconverted peaking I and Q signals to a peaking analog phase-modulated drive signal;

a main switch-mode power amplifier (SMPA) configured to be driven by the main analog phase-modulated drive signal;

a peaking SMPA configured to be driven by the peaking analog phase-modulated drive signal; and

a quarter-wavelength impedance inverter coupled between an output of the main SMPA and the peaking SMPA.