NON-VOLATILE MEMORY WITH A NEW SENSING SEQUENCE CONTROL METHOD

• US 20190214059A1
• Filed: 08/29/2018
• Published: 07/11/2019
• Est. Priority Date: 01/10/2018
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Po, Chen-Hao
• Granted Patent: US 10,410,691 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A non-volatile memory includes a sense amplifier, a switching element and a power switching circuit. A first sub-cell is connected with a word line, a bit line and a source line. A second sub-cell is connected with the word line, an inverted bit line and an inverted source line. During a read cycle, an activation period of the word line contains a first period and a second period. In the first period, the first sub-cell generates a first read current to a first current path, and the second sub-cell generates a second read current to a second current path. The first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.

Claims

1. A non-volatile memory, comprising:

a memory cell array comprising a word line, a bit line, an inverted bit line, a source line and an inverted source line, wherein a first sub-cell of a selected differential cell is connected with the word line, the bit line and the source line, and a second sub-cell of the selected differential cell is connected with the word line, the inverted bit line and the inverted source line;

a sense amplifier comprising a data line and an inverted data line, wherein the sense amplifier generates an output signal and an inverted output signals according to signals from the data line and the inverted data line;

a switching element comprising a first switching circuit and a second switching circuit, wherein the first switching circuit is connected between the data line and the bit line, and the second switching circuit is connected between the inverted data line and the inverted bit line;

a power switching circuit connected with the bit line, the inverted bit line, the source line and the inverted source line,

wherein during a read cycle, an activation period of the word line contains a first period and a second period, wherein in the first period, the first sub-cell generates a first read current to a first current path, which is defined by the data line, the first switching circuit, the bit line, the first sub-cell, the source line and the power switching circuit, wherein in the first period, the second sub-cell generates a second read current to a second current path, which is defined by the inverted data line, the second switching circuit, the inverted bit line, the second sub-cell, the inverted source line and the power switching circuit,

wherein the first current path and the second current path are controlled to be opened according to the correlation of the first read current and the second read current.

2. The non-volatile memory as claimed in claim 1, wherein if the first read current is higher than the second read current, the second current path is opened in the second period, wherein if the second read current is higher than the first read current, the first current path is opened in the second period.

3. The non-volatile memory as claimed in claim 1, wherein the first switching circuit is a first transmission gate, and the second switching circuit is a second transmission gate, wherein a first terminal of the first transmission gate is connected with the bit line, a second terminal of the first transmission gate is connected with the data line, a control terminal of the first transmission gate receives a select signal, and an inverted control terminal of the first transmission gate receives an inverted select signal, wherein a first terminal of the second transmission gate is connected with the inverted bit line, a second terminal of the second transmission gate is connected with the inverted data line, a control terminal of the second transmission gate receives the select signal, and an inverted control terminal of the second transmission gate receives the inverted select signal.

4. The non-volatile memory as claimed in claim 3, wherein the power switching circuit comprises:

a first switch transistor, wherein a first terminal of the first switch transistor receives a power voltage, a second terminal of the first switch transistor is connected with the source line, and a control terminal of the first switch transistor receives a source line enabling signal;

a second switch transistor, wherein a first terminal of the second switch transistor receives the power voltage, a second terminal of the second switch transistor is connected with the inverted source line, and a control terminal of the second switch transistor receives an inverted source line enabling signal;

a first AND gate, wherein a first input terminal of the first AND gate receives a read signal, a second input terminal of the first AND gate receives the output signal, and an output terminal of the first AND gate generates the source line enabling signal;

a second AND gate, wherein a first input terminal of the second AND gate receives the read signal, a second input terminal of the second AND gate receives the inverted output signal, and an output terminal of the second AND gate generates the inverted source line enabling signal;

a third switching circuit connected between the bit line and the source line;

a fourth switching circuit connected between the inverted bit line and the inverted source line, wherein during the read cycle, the third switching circuit and the fourth switching circuit are in an open state;

a third switch transistor, wherein a first terminal of the third switch transistor receives a charging voltage, a second terminal of the third switch transistor is connected with the bit line, and a control terminal of the third switch transistor receives a pre-charge signal; and

a fourth switch transistor, wherein a first terminal of the fourth switch transistor receives the charging voltage, a second terminal of the fourth switch transistor is connected with the inverted bit line, and a control terminal of the fourth switch transistor receives the pre-charge signal.

5. The non-volatile memory as claimed in claim 4, wherein during the read cycle, the read signal is in a high level state, wherein before the activation period, the third switch transistor and the fourth switch transistor are controlled according to the pre-charge signal, so that the bit line and the inverted bit line are pre-charged to the charging voltage, wherein in the activation period, the select signal is in the high level state.

6. The non-volatile memory as claimed in claim 1, wherein the first switching circuit is a first transmission gate, and the second switching circuit is a second transmission gate, wherein a first terminal of the first transmission gate is connected with the bit line, a second terminal of the first transmission gate is connected with the data line, a control terminal of the first transmission gate receives a first control signal, and an inverted control terminal of the first transmission gate receives an inverted first control signal, wherein a first terminal of the second transmission gate is connected with the inverted bit line, a second terminal of the second transmission gate is connected with the inverted data line, a control terminal of the second transmission gate receives a second control signal, and an inverted control terminal of the second transmission gate receives an inverted second control signal.

7. The non-volatile memory as claimed in claim 6, wherein the power switching circuit comprises:

a first switch transistor, wherein a first terminal of the first switch transistor receives a power voltage, a second terminal of the first switch transistor is connected with the source line, and a control terminal of the first switch transistor receives a source line enabling signal;

a second switch transistor, wherein a first terminal of the second switch transistor receives the power voltage, a second terminal of the second switch transistor is connected with the inverted source line, and a control terminal of the second switch transistor receives an inverted source line enabling signal;

a first AND gate, wherein a first input terminal of the first AND gate receives a read signal, a second input terminal of the first AND gate receives the output signal, and an output terminal of the first AND gate generates the source line enabling signal;

a second AND gate, wherein a first input terminal of the second AND gate receives the read signal, a second input terminal of the second AND gate receives the inverted output signal, and an output terminal of the second AND gate generates the inverted source line enabling signal;

a third AND gate, wherein a first input terminal of the third AND gate receives the read signal, a second input terminal of the third AND gate receives a select signal, a third input terminal of the third AND gate receives the output signal, and an output terminal of the third AND gate generates the first control signal;

a fourth AND gate, wherein a first input terminal of the fourth AND gate receives the read signal, a second input terminal of the fourth AND gate receives the select signal, a third input terminal of the fourth AND gate receives the inverted output signal, and an output terminal of the fourth AND gate generates the second control signal;

a first NOT gate, wherein an input terminal of the first NOT gate receives the first control signal, and an output terminal of the first NOT gate generates the inverted first control signal;

a second NOT gate, wherein an input terminal of the second NOT gate receives the second control signal, and an output terminal of the second NOT gate generates the inverted second control signal;

a third switching circuit connected between the bit line and the source line;

a fourth switching circuit connected between the inverted bit line and the inverted source line, wherein during the read cycle, the third switching circuit and the fourth switching circuit are in an open state;

a third switch transistor, wherein a first terminal of the third switch transistor receives a charging voltage, a second terminal of the third switch transistor is connected with the bit line, and a control terminal of the third switch transistor receives a pre-charge signal; and

a fourth switch transistor, wherein a first terminal of the fourth switch transistor receives the charging voltage, a second terminal of the fourth switch transistor is connected with the inverted bit line, and a control terminal of the fourth switch transistor receives the pre-charge signal.

8. The non-volatile memory as claimed in claim 7, wherein during the read cycle, the read signal is in a high level state, wherein before the activation period, the third switch transistor and the fourth switch transistor are controlled according to the pre-charge signal, so that the bit line and the inverted bit line are pre-charged to the charging voltage, wherein in the activation period, the select signal is in the high level state.

9. The non-volatile memory as claimed in claim 6, wherein the power switching circuit comprises:

a first AND gate, wherein a first input terminal of the first AND gate receives a read signal, a second input terminal of the first AND gate receives a select signal, a third input terminal of the first AND gate receives the output signal, and an output terminal of the first AND gate generates the first control signal;

a second AND gate, wherein a first input terminal of the second AND gate receives the read signal, a second input terminal of the second AND gate receives the select signal, a third input terminal of the second AND gate receives the inverted output signal, and an output terminal of the second AND gate generates the second control signal;

a first NOT gate, wherein an input terminal of the first NOT gate receives the first control signal, and an output terminal of the first NOT gate generates the inverted first control signal;

a second NOT gate, wherein an input terminal of the second NOT gate receives the second control signal, and an output terminal of the second NOT gate generates the inverted second control signal;

a third switching circuit connected between the bit line and the source line, wherein the source line receives a power voltage;

a fourth switching circuit connected between the inverted bit line and the inverted source line, wherein the inverted source line receives the power voltage, wherein during the read cycle, the third switching circuit and the fourth switching circuit are in an open state;

a third switch transistor, wherein a first terminal of the third switch transistor receives a charging voltage, a second terminal of the third switch transistor is connected with the bit line, and a control terminal of the third switch transistor receives a pre-charge signal; and

a fourth switch transistor, wherein a first terminal of the fourth switch transistor receives the charging voltage, a second terminal of the fourth switch transistor is connected with the inverted bit line, and a control terminal of the fourth switch transistor receives the pre-charge signal.

10. The non-volatile memory as claimed in claim 9, wherein during the read cycle, the read signal is in a high level state, wherein before the activation period, the third switch transistor and the fourth switch transistor are controlled according to the pre-charge signal, so that the bit line and the inverted bit line are pre-charged to the charging voltage, wherein in the activation period, the select signal is in the high level state.