CODE RATE SWITCHING MECHANISM FOR FLASH MEMORY

• US 20190215016A1
• Filed: 01/11/2018
• Published: 07/11/2019
• Est. Priority Date: 01/11/2018
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: COMETTI, Aldo Giovanni, DURGAM, Aniryudh Reddy
• Granted Patent: US 10,644,727 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/353 Adaptation to the channel

Abstract

A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.

Claims

1. A method comprising:

setting a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device;

receiving, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate; and

switching the set code rate from the first code rate to the second code rate at the indicated switch point.

2. The method of claim 1, wherein the first code rate is higher than the second code rate.

3. The method of claim 1, further comprising:

reading and decoding data encoded at the first code rate from the non-volatile memory in response to switching the set code rate from the first code rate to the second code rate;

encoding the read and decoded data at the second code rate; and

writing the data encoded at the second code rate to the non-volatile memory.

4. The method of claim 1, wherein the indicated switch point is time at which the host command is received.

5. The method of claim 1, further comprising:

determining that the indicated switch point has been reached in the non-volatile memory,

wherein the set code rate is switched from the first code rate to the second code rate in response to determining that the indicated switch point has been reached.

6. The method of claim 5, wherein the indicated switch point is a program-erase cycle threshold, and

wherein determining that the indicated switch point has been reached comprises determining that a program-erase cycle count of the non-volatile memory satisfies the program-erase cycle threshold.

7. The method of claim 6, wherein the program-erase cycle threshold is based on an offline duration specification of the data storage device.

8. A data storage device comprising:

non-volatile memory; and

a controller coupled to the non-volatile memory, the controller configured to;

set a code rate in the data storage device to a first code rate for encoding data to be written to the non-volatile memory;

receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate;

determine that the indicated switch point has been reached in the non-volatile memory; and

switch the set code rate from the first code rate to the second code rate in response to determining that the indicated switch point has been reached.

9. The data storage device of claim 8, wherein the controller is further configured to:

read and decode data encoded at the first code rate from the non-volatile memory in response to switching the set code rate from the first code rate to the second code rate;

encode the read and decoded data at the second code rate; and

write the data encoded at the second code rate to the non-volatile memory.

10. The data storage device of claim 8, wherein the first code rate is higher than the second code rate.

11. The data storage device of claim 8, wherein the indicated switch point is a program-erase cycle threshold, and

wherein the controller is configured to determine that the indicated switch point has been reached by determining that a program-erase cycle count of the non-volatile memory satisfies the program-erase cycle threshold.

12. The data storage device of claim 11, wherein the program-erase cycle threshold is based on an offline duration specification of the data storage device.

13. A non-transitory, processor-readable storage media encoded with instructions that, when executed by processor, perform a method comprising:

setting a code rate to a first code rate for encoding data to be written to non-volatile memory of a data storage device;

receiving a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate;

switching the set code rate from the first code rate to the second code rate at the indicated switch point;

reading and decoding data encoded at the first code rate from the non-volatile memory in response to switching the set code rate from the first code rate to the second code rate;

encoding the read and decoded data at the second code rate; and

writing the data encoded at the second code rate to the non-volatile memory.

14. The processor-readable storage media of claim 13, wherein the first code rate is higher than the second code rate.

15. The processor-readable storage media of claim 13, wherein the indicated switch point is time at which the host command is received.

16. The method of claim 15, wherein the method further comprises:

determining that the indicated switch point has been reached in the non-volatile memory,

wherein the set code rate is switched from the first code rate to the second code rate in response to determining that the indicated switch point has been reached.

17. The processor-readable storage media of claim 16, wherein the indicated switch point is a program-erase cycle threshold, and

wherein the set code rate is switched from the first code rate to the second rate in response to determining that a number of program-erase cycles of the non-volatile memory has reached the program-erase cycle threshold.

18. The processor-readable storage media of claim 17, wherein the program-erase cycle threshold is based on an offline duration of the data storage device.

19. A data storage device comprising:

non-volatile memory;

means for setting a code rate in the data storage device to a first code rate for encoding data to be written to the non-volatile memory;

means for receiving, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate;

means for determining that the indicated switch point has been reached in the non-volatile memory; and

means for switching the set code rate from the first code rate to the second code rate in response to determining that the indicated switch point has been reached.

20. The data storage device of claim 19, wherein the first code rate is higher than the second code rate.

21. The data storage device of claim 19, wherein the data storage device further comprises:

means for reading and decoding data encoded at the first code rate from the non-volatile memory in response to switching the set code rate from the first code rate to the second code rate;

means for encoding the read and decoded data at the second code rate; and

means for writing the data encoded at the second code rate to the non-volatile memory.

22. The data storage device of claim 19, wherein the indicated switch point is a program-erase cycle threshold, and

wherein the means for switching the set code rate is configured to switch the set code rate from the first code rate to the second rate in response to determining that a number of program-erase cycles of the non-volatile memory has reached the program-erase cycle threshold.