Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence
First Claim
1. A circuit on a chip for serial data applications, the circuit comprising:
- a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and
a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including an out-of-band parasitic pole, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor in combination with the out-of-band parasitic pole configured to suppress quantization noise introduced by modulating the frac-N PLL.
10 Assignments
0 Petitions
Accused Products
Abstract
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
-
Citations
34 Claims
-
1. A circuit on a chip for serial data applications, the circuit comprising:
-
a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including an out-of-band parasitic pole, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor in combination with the out-of-band parasitic pole configured to suppress quantization noise introduced by modulating the frac-N PLL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A circuit on a chip for serial data applications, the circuit comprising:
-
a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to produce an on-chip reference clock signal; and a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including a divider with a divide value, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor configured to suppress a portion of quantization noise, the portion introduced by modulating the divide value of the divider of the frac-N PLL. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
-
-
24. A circuit on a chip for serial data applications, the circuit comprising:
-
a common phase-locked loop (PLL), the common PLL configured to produce an on-chip reference clock signal; and a serializer/deserializer (SerDes) lane including a fractional-N (frac-N) PLL, the frac-N PLL including a sigma-delta modulator, the on-chip reference clock signal distributed to the frac-N PLL, the frac-N PLL configured to have an order that is lower relative to that of the sigma-delta modulator of the frac-N PLL of the SerDes lane. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
-
Specification