High Frame Rate Display

• US 20190228726A1
• Filed: 03/29/2019
• Published: 07/25/2019
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Ono, Shinya, Lee, Zino, Choo, Gihoon, Edrees, Hassan, Lin, Chin-Wei
• Granted Patent: US 11,211,020 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

Claims

1. A display, comprising:

an array of display pixels arranged in rows and columns;

an odd data line that is coupled to display pixels in odd rows within a given column of display pixels in the array;

an even data line that is coupled to display pixels in even rows within the given column of display pixels in the array, wherein the odd data line is formed on a first side of the given column, and wherein the even data line is formed on a second side of the given column that is different than the first side to reduce vertical data line crosstalk; and

demultiplexer circuitry coupled to the odd and even data lines, wherein the demultiplexer circuitry is configured to provide data signals to a selected one of the odd and even data lines.

2. The display of claim 1, wherein the odd and even data lines are formed on opposing sides of the given column of display pixels.

3. The display of claim 1, wherein the display pixels in the odd rows in the given column have a different orientation than the display pixels in the even rows in the given column.

4. The display of claim 3, wherein the display pixels in the odd rows in the given column mirrored with respect to the display pixels in the even rows in the given column.

5. The display of claim 1, further comprising:

an additional odd data line that is coupled to display pixels in the odd rows within an additional column of display pixels in the array; and

an additional even data line that is coupled to display pixels in the even rows within the additional column of display pixels in the array, wherein the demultiplexer circuitry is also coupled to the additional odd data line and the additional even data line.

6. The display of claim 5, wherein the additional even data line is formed closer to the even data line than the additional odd data line.

7. The display of claim 5, wherein the additional odd data line is formed closer to the odd data line than the additional even data line.

8. The display of claim 5, wherein the display pixels in the given column have a different orientation than the display pixels in the additional column.

9. The display of claim 8, wherein the display pixels in the given column mirrored with respect to the display pixels in the additional column.

10. The display of claim 1, wherein the demultiplexer circuitry comprises:

a first transistor coupled between a driver circuit and the odd data line; and

a second transistor coupled between the driver circuit and the even data line, wherein the first transistor is configured to receive an odd selection signal, and wherein the second transistor is configured to receive an even selection signal.

11. A method of operating a display that includes at least one column of pixels that is coupled to an odd data line and an even data line, the method comprising:

driving a first data signal onto the odd data line;

asserting a first gate line signal to access a selected pixel in the column of pixels;

allowing the data line to be in a high impedance state; and

while the data line is in the high impedance state, driving a second data signal onto the even data line, wherein a corresponding voltage change on the even data line caused by the second data signal is not coupled to the odd data line.

12. The method of claim 11, wherein asserting the first gate line signal comprises loading the first data signal from the odd data line into the selected pixel.

13. The method of claim 12, further comprising asserting a second gate line signal to access an additional pixel in the column of pixels.

14. The method of claim 13, wherein asserting the second gate line signal comprises loading the second data signal from the even data line into the additional pixel.

15. The method of claim 13, wherein the selected pixel includes a first data loading transistor, wherein the additional pixel includes a second data loading transistor, wherein the first data loading transistor is separated from the odd data line by a first distance and wherein the second data loading transistor is separated from the even data line by a second distance that is equal to the first distance.

16. The method of claim 11, wherein the odd and even data lines are not immediately adjacent to each other.

17. A display comprising:

a column of pixels;

a first data line that is formed on one side of the column, wherein the first data line is coupled to pixels in the odd rows of the column; and

a second data line that is formed on another side of the column, wherein the second data line is coupled to pixels in the even rows of the column.

18. The display of claim 17, wherein the pixels in the odd rows have a different orientation than the pixels in the even rows.

19. The display of claim 17, wherein only one of the first and second data lines is actively driven at any point in time during operation of the display.

20. The display of claim 17, wherein the pixels in the odd rows of the column exhibit a first amount of parasitic capacitance to the odd data line, and wherein the pixels in the even rows of the column exhibit a second amount of parasitic capacitance to the even data line that is equal to the first amount of parasitic capacitance.