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DUAL-GATE PMOS FIELD EFFECT TRANSISTOR WITH InGaAs CHANNEL

  • US 20190229182A1
  • Filed: 12/28/2016
  • Published: 07/25/2019
  • Est. Priority Date: 10/12/2016
  • Status: Active Grant
First Claim
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1. A Field Effect Transistor (FET), comprising:

  • a bottom gate structure;

    an InGaAs channel layer;

    a top gate structure; and

    a lower interface control layer and an upper interface control layer,wherein the lower interface control layer is disposed between the bottom gate structure and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate structure and the InGaAs channel layer.

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