SEALED CAVITY STRUCTURES WITH A PLANAR SURFACE

• US 20190229185A1
• Filed: 01/22/2018
• Published: 07/25/2019
• Est. Priority Date: 01/22/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: ADUSUMILLI, Siva P., STAMPER, Anthony K., SCHUTZ, Laura J., Luce, Cameron E.
• Granted Patent: US 10,446,643 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

Claims

1. A structure comprising a cavity formed in a substrate material, the cavity being covered with epitaxial material that has an upper planar surface, wherein the cavity comprises a trench which includes a curvature at its open end and which is under a transistor.

3. The structure of claim 1, further comprising a trench which extends from the cavity to a surface of the substrate material, wherein the cavity is under the trench.

4. The structure of claim 1, wherein the epitaxial material is a reflowed SiGe material and upper Si sealing layer.

5. The structure of claim 4, further comprising a transistor formed on the upper planar surface of the Si sealing layer, above the cavity.

6. The structure of claim 1, wherein the cavity is only under a source region and a drain region of a gate structure on the planar surface.

7. The structure of claim 1, wherein the cavity is under source and drain regions extending partially but not completely under the gate on the planar surface.

8. The structure of claim 1, wherein the cavity is only under a gate structure on the planar surface.

9. The structure of claim 1, wherein the cavity is under a gate structure on the planar surface and extends partially under source/drain regions of the gate structure.

10. The structure of claim 1, wherein a depletion region under source/drain regions of a gate structure on the planar surface is intersected by the cavity.

11. The structure of claim 1, wherein a triple well under the gate structure on the planar surface is intersected by the cavity.

12. The structure of claim 1, further comprising a plurality of cavities which are merged together and which are formed under a sealing layer and which are parallel and/or perpendicular to gate structures.

2. (canceled)

13. A structure comprising:

a substrate material;

a cavity formed in the substrate which includes a trench having a curved edge portion at its upper end;

a first material within the trench which migrates to the upper end of the trench; and

a second material which covers the first material and which covers the trench, the second material having a planar surface

wherein the first material is SiGe, the second material is Si material, the SiGe has a Ge concentration of about 5-30%, and after reflow, the SiGe has a top surface that is flat.

15. The structure of claim 13, wherein the first material has characteristics that allow it to reflow during the deposition of the Si material.

16. The structure of claim 13, further comprising a transistor formed on the planar surface of the second material.

14. (canceled)

17. A structure comprising:

a substrate material;

a cavity formed in the substrate which includes a trench having a curved edge portion at its upper end;

a first material within the trench which migrates to the upper end of the trench; and

a second material which covers the first material and which covers the trench, the second material having a planar surface;

a gate structure with a source region and a drain region, wherein the cavity is under one of;

only the source region and the drain region;

the source region and the drain region and extends under the gate structure;

only under the gate structure on the planar surface; and

the gate structure and extends partially under the source region and the drain region.

18-20. -20. (canceled)