ANNEALED SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY

• US 20190237659A1
• Filed: 02/01/2018
• Published: 08/01/2019
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: ANNUNZIATA, Anthony J., KOTHANDARAMAN, Chandrasekharan, NOWAK, Janusz J., O'SULLIVAN, Eugene J.
• Granted Patent: US 10,700,263 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a seed layer on and in contact with a semiconductor structure;

annealing the seed layer;

planarizing the seed layer after the seed layer has been annealed; and

forming a magnetic tunnel junction stack on and in contact with the seed layer after the seed layer has been planarized.

2. The method of claim 1, wherein the annealing is performed at a temperature ranging from 200°

C. to 400°

C.

3. The method of claim 1, wherein the seed layer is planarized to have a Root Mean Square surface roughness ranging from 1 Angstrom to 3 Angstroms.

4. The method of claim 1, further comprising:

forming at least one trench within a substrate; and

forming a pad layer on and in contact with the at least one trench line, wherein the semiconductor structure is comprised of the at least one trench and the pad layer.

5. The method of claim 4, wherein the seed layer is formed on and in contact with the pad layer.

6. The method of claim 1, wherein forming the magnetic tunnel junction stack comprises:

depositing magnetic tunnel junction stack layers on and in contact with the seed layer; and

etching the magnetic tunnel junction stack layers to form the magnetic tunnel junction stack.

7. The method of claim 6, wherein etching the magnetic tunnel junction stack layers to form the magnetic tunnel junction stack comprises:

forming a hardmask on the magnetic tunnel junction stack layers; and

etching portions of the magnetic tunnel junction stack layers not underlying the hardmask.

8-20. -20. (canceled)