SERIALIZER AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

• US 20190238156A1
• Filed: 08/07/2018
• Published: 08/01/2019
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Young-Hoon
• Granted Patent: US 10,644,722 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/356095 with synchronous operation
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor
• CPC Class Codes: H04Q 2213/036 Series parallel conversion; Parallel bit transmission

Abstract

A serializer includes: a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.

Claims

1. A serializer, comprising:

a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data;

a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and

an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.

2. The serializer of claim 1, wherein the hybrid multiplexing circuit includes:

a static logic unit suitable for generating the pull-down control signal by removing the input loading of the aligned data, and generating the pull-up control signal by removing the input loading of the complementary aligned data; and

a dynamic logic unit suitable for outputting the pull-down signal and the pull-up signal that are selectively driven based on the pull-down control signal and the pull-up control signal.

3. The serializer of claim 2, wherein when all the aligned data come to be at a first logic level, the static logic unit outputs the pull-down control signal at a first logic level, and

when all the complementary aligned data come to be at the first logic level, the static logic unit outputs the pull-up control signal at the first logic level.

4. The serializer of claim 2, wherein the static logic unit includes:

a plurality of first logic gates suitable for performing a logic NAND operation onto two adjacent data among the aligned data;

a second logic gate suitable for outputting the pull-down control signal by performing a logic NOR operation onto outputs of the first logic gates;

a plurality of third logic gates suitable for performing a logic NAND operation onto two adjacent data among the complementary aligned data; and

a fourth logic gate suitable for outputting the pull-up control signal by performing a logic NOR operation onto outputs of the third logic gates.

5. The serializer of claim 2, wherein the dynamic logic unit includes:

a first drive controller suitable for driving a first output signal based on the pull-down control signal and the pull-up control signal;

a first latch suitable for outputting the pull-down signal by inverting and latching the first output signal;

a second drive controller suitable for driving a second output signal based on the pull-down control signal and the pull-up control signal; and

a second latch suitable for outputting the pull-up signal by inverting and latching the second output signal.

6. The serializer of claim 5, wherein the first drive controller includes:

a first pull-up transistor that is coupled between a power source voltage terminal and a first output node that outputs the first output signal, and receives the pull-down control signal through a gate; and

a first pull-down transistor that is coupled between a ground voltage terminal and the first output node, and receives an inverted signal of the pull-up control signal through a gate.

7. The serializer of claim 5, wherein the second drive controller includes:

a second pull-up transistor that is coupled between a power source voltage terminal and a second output node that outputs the second output signal, and receives the pull-up control signal through a gate; and

a second pull-down transistor that is coupled between a ground voltage terminal and the second output node, and receives an inverted signal of the pull-down control signal through a gate.

8. The serializer of claim 1, wherein the clocks have a phase difference which is obtained by dividing 360 degrees (9 by the number of input data, and

the data trigger circuit differentially amplifies the input data based on adjacent clocks among the clocks, and outputs the aligned data and the complementary aligned data.

9. The serializer of claim 8, wherein the data trigger circuit differentially amplifies the input data and outputs the aligned data and the complementary aligned data in a first section in which the adjacent clocks have a predetermined logic level, and

the data trigger circuit pre-charges the aligned data and the complementary aligned data at the first logic level in a second section which is not the first period.

10. The serializer of claim 1, wherein the data trigger circuit includes a plurality of trigger units corresponding to the input data, and

each of the trigger units includes:

an initializer suitable for initializing a first node which outputs the aligned data and a second node which outputs the complementary aligned data in response to a first clock and a second clock;

a charge discharger suitable for receiving the input data and discharging charges from the first node and the second node in response to the first clock and the second clock; and

a charge supplier suitable for selectively supplying charges to the first node and the second node based on logic levels of the first node and the second node.

11. The serializer of claim 10, wherein the charge discharger selectively discharges the changes from the first node and the second node based on the logic level of the corresponding input data in a section where the first clock and the second clock are at predetermined logic levels.

12. A semiconductor system, comprising:

a first semiconductor device; and

a second semiconductor device suitable for serially communicating with the first semiconductor device through a transfer line,

wherein each of the first semiconductor device and the second semiconductor device includes the transfer line for converting parallel internal data into a serial data, and

the transfer line includes;

a data trigger circuit suitable for latching the internal data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data;

a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively driven based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and

an output driver suitable for outputting the serial data corresponding to the pull-up signal and the pull-down signal.

13. The semiconductor system of claim 12, wherein the hybrid multiplexing circuit includes:

a static logic unit suitable for generating the pull-down control signal by removing the input loading of the aligned data, and generating the pull-up control signal by removing the input loading of the complementary aligned data; and

a dynamic logic unit suitable for outputting the pull-down signal and the pull-up signal that are selectively driven based on the pull-down control signal and the pull-up control signal.

14. The semiconductor system of claim 13, wherein the static logic unit includes:

a plurality of first logic gates suitable for performing a logic NAND operation onto two adjacent data among the aligned data;

a second logic gate suitable for outputting the pull-down control signal by performing a logic NOR operation onto outputs of the first logic gates;

a plurality of third logic gates suitable for performing a logic NAND operation onto two adjacent data among the complementary aligned data; and

a fourth logic gate suitable for outputting the pull-up control signal by performing a logic NOR operation onto outputs of the third logic gates.

15. The semiconductor system of claim 13, wherein the dynamic logic unit includes:

a first drive controller suitable for driving a first output signal based on the pull-down control signal and the pull-up control signal;

a first latch suitable for outputting the pull-down signal by inverting and latching the first output signal;

a second drive controller suitable for driving a second output signal based on the pull-down control signal and the pull-up control signal; and

a second latch suitable for outputting the pull-up signal by inverting and latching the second output signal.

16. The semiconductor system of claim 15, wherein the first drive controller includes:

a first pull-up transistor that is coupled between a power source voltage terminal and a first output node that outputs the first output signal, and receives the pull-down control signal through a gate; and

a first pull-down transistor that is coupled between a ground voltage terminal and the first output node, and receives an inverted signal of the pull-up control signal through a gate.

17. The semiconductor system of claim 15, wherein the second drive controller includes:

a second pull-up transistor that is coupled between a power source voltage terminal and a second output node that outputs the second output signal, and receives the pull-up control signal through a gate; and

a second pull-down transistor that is coupled between a ground voltage terminal and the second output node, and receives an inverted signal of the pull-down control signal through a gate.

18. The semiconductor system of claim 12, wherein the clocks have a phase difference which is obtained by dividing 360 degrees)(°

by the number of internal data, and

the data trigger circuit differentially amplifies the internal data based on adjacent clocks among the clocks, and outputs the aligned data and the complementary aligned data.

19. The semiconductor system of claim 18, wherein the data trigger circuit differentially amplifies the internal data and outputs the aligned data and the complementary aligned data in a first section in which the adjacent clocks have a predetermined logic level, and

the data trigger circuit pre-charges the aligned data and the complementary aligned data at the first logic level in a second section which is not the first period.

20. The semiconductor system of claim 19, wherein the data trigger circuit includes a plurality of trigger units corresponding to the internal data, and

each of the trigger units includes:

an initializer suitable for initializing a first node which outputs the aligned data and a second node which outputs the complementary aligned data in response to a first clock and a second clock;

a charge discharger suitable for receiving the internal data and discharging charges from the first node and the second node in response to the first clock and the second clock; and

a charge supplier suitable for selectively supplying charges to the first node and the second node based on logic levels of the first node and the second node.