Method And System For Split Voltage Domain Receiver Circuits

• US 20190238374A1
• Filed: 04/09/2019
• Published: 08/01/2019
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Luxtera Incorporated (Cisco Systems, Inc.)
• Inventors: Welch, Brian
• Granted Patent: US 10,523,477 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 6/4201 Packages, e.g. shape, construction, internal or external details
• CPC Class Codes: G02B 6/4242 Mounting of the optical light guide to the lid of the package
• CPC Class Codes: H04B 10/501 Structural aspects
• CPC Class Codes: H04B 10/516 Details of coding or modulation
• CPC Class Codes: H04B 10/564 Power control
• CPC Class Codes: H04B 10/60 Receivers
• CPC Class Codes: H04B 10/693 Arrangements for optimizing the preamplifier in the receiver
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.

Claims

1. A method for processing signals, the method comprising:

in an integrated circuit;

amplifying a received electrical signal using transistors operating in different partial voltage domains; and

combining output signals from said transistors, utilizing a stacked cascode amplifier for each partial voltage domain, into a single differential signal in a single voltage domain, wherein each of said partial voltage domains is offset by a DC voltage from other of said partial voltage domains.

2. The method according to claim 1, comprising receiving said electrical signal from a photodiode monitored in a complementary mode.

3. The method according to claim 2, wherein said photodiode is integrated in said integrated circuit.

4. The method according to claim 1, comprising combining said amplified received signal via stacked common source amplifiers.

5. The method according to claim 1, comprising combining said amplified received signal via stacked common emitter amplifiers.

6. The method according to claim 1, wherein said received electrical signal is DC coupled to said transistors.

7. The method according to claim 1, comprising DC coupling said output signals prior to said combining.

8. The method according to claim 1, comprising AC coupling said output signals prior to said combining.

9. The method according to claim 1, comprising amplifying and combining said received signal via cascode amplifiers.

10. The method according to claim 1, wherein said voltage domains are stacked.

11. The method according to claim 10, comprising controlling said stacked voltage domains via feedback loops.

12. A system for processing signals, the system comprising:

in an integrated circuit, one or more circuits operable to amplify a received electrical signal using transistors operating in different partial voltage domains; and

said one or more circuits being operable to combine output signals from said transistors into a single differential signal in a single voltage domain utilizing a stacked cascode amplifier for each partial voltage domain, wherein each of said partial voltage domains is offset by a DC voltage from other of said partial voltage domains.

13. The system according to claim 12, wherein said one or more circuits are operable to receive said electrical signal from a photodiode monitored in a complementary mode.

14. The system according to claim 13, wherein said photodiode is integrated in said integrated circuit.

15. The system according to claim 12, wherein said one or more circuits are operable to combine said output signals via stacked common source amplifiers.

16. The system according to claim 12, wherein said one or more circuits combine said output signals via stacked common emitter amplifiers.

17. The system according to claim 12, wherein said received electrical signal is DC coupled to said transistors.

18. The system according to claim 12, wherein said one or more circuits are operable to DC couple said output signals prior to said combining.

19. The system according to claim 12, wherein said one or more circuits are operable to AC couple said output signals prior to said combining.

20. The system according to claim 12, wherein said one or more circuits are operable to amplify and combine said received electrical signal via cascode amplifiers.

21. The system according to claim 12, wherein said voltage domains are stacked.

22. The system according to claim 12 wherein said one or more circuits are operable to control said stacked voltage domains via feedback loops.