VERIFYING PLANARIZATION PERFORMANCE USING ELECTRICAL MEASURES

• US 20190243927A1
• Filed: 02/06/2018
• Published: 08/08/2019
• Est. Priority Date: 02/06/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lallement, Romain, Sieg, Stuart A.
• Granted Patent: US 10,642,950 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

Claims

1. A computer-implemented method for verifying planarization performance using electrical measures, the computer-implemented method comprising:

modeling, using a processor, a planarization layer for a topography of a device;

designing a chip including one or more structures of a design;

measuring electrical characteristics of the one or more structures;

comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures;

applying the planarization model to the one or more structures; and

correlating the measured electrical characteristics to the planarization layer.

2. The computer-implemented method of claim 1, wherein a process for fabricating the device is modified based at least in part on a result of the correlation.

3. The computer-implemented method of claim 1, wherein the modeling includes:

varying a depth-of-focus to measure a critical dimension of a known structure;

determining a reference curve for the known structure;

measuring a critical dimension of the one or more structures of the design; and

comparing the measured critical dimension of the one or more structures to the determined reference curve for the known structure.

4. The computer-implemented method of claim 1, wherein comparing includes:

fitting a critical dimension for each of the one or more structures on the reference curve; and

determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

5. The computer-implemented method of claim 1, wherein comparing includes:

determining a curve for each of the one or more structures of the design; and

comparing each curve for each of the one or more structures to the reference curve.

6. The computer-implemented method of claim 1, wherein the measuring includes measuring a gate length of each of the one or more structures.

7. The computer-implemented method of claim 1, wherein the measuring includes measuring metal height of each of the one or more structures.

8. The computer-implemented method of claim 1, wherein the measuring includes measuring a gate length of each of the one or more structures.

9. The computer-implemented method of claim 1, wherein the planarization layer is an organic planarization layer.

10. A system for verifying planarization performance using electrical measures, the system comprising:

storage medium, the storage medium being communicatively coupled to a processor;

the processor configured to;

model a planarization layer for a topography of a device;

design a chip including one or more structures;

collect measured electrical characteristics of the one or more structures;

compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures;

apply the planarization model to the one or more structures; and

correlate the measured electrical characteristics to the planarization layer.

11. The system of claim 10, wherein a process for fabricating the device is modified based at least in part on a result of the correlation.

12. The system of claim 10, wherein the modeling includes varying a depth-of-focus to measure a critical dimension of a known structure;

determining a reference curve for the known structure;

measuring a critical dimension of the one or more structures; and

comparing the measured critical dimension of the one or more structures of the design to the determined reference curve for the known structure.

13. The system of claim 10, wherein comparing includes fitting a critical dimension for each of the one or more structures on the reference curve;

and

determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

14. The system of claim 10, wherein the comparing includes determining a curve for each of the one or more structures of the design;

and

comparing each curve for each of the one or more structures to the reference curve.

15. The system of claim 10, wherein the planarization layer is an organic planarization layer.

16. A computer program product for verifying planarization performance using electrical measurements, the computer program product comprising:

a computer readable storage medium having stored thereon program instructions executable by a processor to cause the processor to;

model a planarization layer for a topography of a device;

design a chip including one or more structures;

collect measured electrical characteristics of the one or more structures;

compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures;

apply the planarization model to the one or more structures; and

correlate the measured electrical characteristics to the planarization layer.

17. The computer program product of claim 16, wherein a process for fabricating the device is modified based at least in part on a result of the correlation.

18. The computer program product of claim 16, wherein the modeling includes varying a depth-of-focus to measure a critical dimension of a known structure;

determining a reference curve for the known structure;

measuring a critical dimension of the one or more structures of the design; and

comparing the measured critical dimension of the one or more structures to the determined reference curve for the known structure.

19. The computer program product of claim 16, wherein comparing includes fitting a critical dimension for each of the one or more structures on the reference curve;

and

determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

20. The computer program product of claim 16, wherein the comparing includes determining a curve for each of the one or more structures;

and

comparing each curve for each of the one or more structures to the reference curve.