METAL-ON-METAL CAPACITORS

• US 20190244894A1
• Filed: 02/06/2018
• Published: 08/08/2019
• Est. Priority Date: 02/06/2018
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fu, Yi Chun A., Keramat, Mansour, Srinivas, Vijay
• Granted Patent: US 10,453,791 B2
• Time in Patent Office: Days
• CPC Class Codes: H01G 4/01 Form of self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H03M 1/20 Increasing resolution using an n bit system to obtain n + m bits
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

Claims

1. A capacitor structure comprising:

an array of capacitor unit cells surrounded by a plurality of border unit cells;

each capacitor unit cell comprises a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes;

each border unit cell comprises a first plurality of dummy finger electrodes interdigitated with a second plurality of dummy finger electrodes; and

wherein the first and second plurality of finger electrodes are pitched-matched across the array of capacitor unit cells, and the first and second plurality of dummy finger electrodes are pitch-matched with the first and second plurality of finger electrodes.

2. The capacitor structure of claim 1, wherein the first and second plurality of dummy finger electrodes are characterized by having same dimensions and pitch as the first and second pluralities of finger electrodes.

3. The capacitor structure of claim 2, wherein the first and second plurality of dummy finger electrodes are electrically grounded.

4. The capacitor structure of claim 2, wherein each capacitor unit cell further comprises a third plurality of finger electrodes interdigitated with a fourth plurality of finger electrodes, each of the first and second plurality of finger electrodes are within a lower metal layer, and each of the third and fourth plurality of finger electrodes are within an upper metal layer, wherein the third and fourth pluralities of finger electrodes are orthogonal to the first and second pluralities of finger electrodes.

5. The capacitor structure of claim 4, wherein the array of capacitor unit cells comprises a plurality of capacitor main unit cells, and a plurality of capacitor sub-unit cells, each capacitor main unit cell and each capacitor sub-unit cell characterized by an approximately equivalent via density between the lower metal layer and the upper metal layer.

6. The capacitor structure of claim 5, wherein each border unit cell comprises vias between the low metal layer and the upper metal layer, the border unit cell vias characterized by the approximately equivalent via density

7. The capacitor structure of claim 4, wherein the first array of finger electrodes comprises a common lower rail extending through a first series of capacitor unit cells within the array of capacitor unit cells, wherein a corresponding series of the first array of finger electrodes and the third array of finger electrodes are electrically connected to the common lower rail.

8. The capacitor structure of claim 7, wherein the fourth array of finger electrodes comprises a common upper rail extending through a second series of capacitor unit cells within the array of capacitor unit cells, and a corresponding series of the fourth array of finger electrodes and the second array of finger electrodes are electrically connected to the common upper rail.

9. The capacitor structure of claim 7, wherein the common lower rail extends through a first border unit cell, and the common upper rail extends through a second border unit cell.

10. The capacitor structure of claim 4, further comprising a polysilicon layer below the lower metal layer, the polysilicon layer including a fifth plurality of finger electrodes interdigitated with a sixth plurality of finger electrodes, wherein the first, second, fifth, and sixth pluralities of finger electrodes are orthogonal to the third and fourth pluralities of finger electrodes.

11. A capacitor structure comprising:

a lower metal layer including a first array of finger electrodes interdigitated with a second array of finger electrodes within a corresponding array of capacitor unit cells;

an upper metal layer including a third array of finger electrodes interdigitated with a fourth array of finger electrodes within the array of capacitor unit cells, wherein the first and second arrays of finger electrodes are orthogonal to the third and fourth arrays of finger electrodes;

wherein the first array of finger electrodes comprises a common lower rail extending through a first series of capacitor unit cells within the array of capacitor unit cells, wherein a corresponding series of the first array of finger electrodes and the third array of finger electrodes are electrically connected to the common lower rail; and

wherein the fourth array of finger electrodes comprises a common upper rail extending through a second series of capacitor unit cells within the array of capacitor unit cell, and a corresponding series of the fourth array of finger electrodes and the second array of finger electrodes are electrically connected to the common upper rail.

12. The capacitor structure of claim 11, wherein the second series of capacitor unit cells is orthogonal to the first series of capacitor unit calls.

13. The capacitor structure of claim 11, wherein the array of capacitor unit cells is surrounded by a plurality of border unit cells.

14. The capacitor structure of claim 13, wherein the common lower rail extends through a first border unit cell.

15. The capacitor structure of claim 14, wherein the common upper rail extends through a second border unit cell.

16. The capacitor structure of claim 15, wherein each border unit cell comprises an arrangement of metal lines lower and upper metal layers that is pitch-matched with first, second, third, and fourth arrays of finger electrodes.

17. A capacitor structure comprising:

a lower metal layer including a first array of finger electrodes interdigitated with a second array of finger electrodes within a corresponding array of capacitor unit cells;

an upper metal layer including a third array of finger electrodes interdigitated with a fourth array of finger electrodes within the array of capacitor unit cells; and

a polysilicon layer below the lower metal layer, the polysilicon layer including a fifth array of finger electrodes interdigitated with a sixth array of finger electrodes;

wherein the first, second, fifth, and sixth arrays of finger electrodes are orthogonal to the third and fourth arrays of finger electrodes.

18. The capacitor structure of claim 17, wherein fifth array of finger electrodes is coupled to ground, and the sixth array of finger electrodes is coupled to power.

19. The capacitor structure of claim 17, wherein the first array of finger electrodes comprises a common lower rail extending through a first series of capacitor unit cells within the array of capacitor unit cells, wherein a corresponding series of the first array of finger electrodes and the third array of finger electrodes are electrically connected to the common lower rail.

20. The capacitor structure of claim 19, wherein the fourth array of finger electrodes comprises a common upper rail extending through a second series of capacitor unit cells within the array of capacitor unit cell, and a corresponding series of the fourth array of finger electrodes and the second array of finger electrodes are electrically connected to the common upper rail.