SEMICONDUCTOR DEVICE INCLUDING VIA PLUG AND METHOD OF FORMING THE SAME

• US 20190244896A1
• Filed: 06/14/2018
• Published: 08/08/2019
• Est. Priority Date: 02/07/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Eui Bok, BAEK, Jong Min, AHN, Sang Hoon, OH, Hyeok Sang
• Granted Patent: US 10,461,027 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02172 the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides materials containing silicon H01L21/02123; metal silicates H01L21/02142
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.

Claims

1. A semiconductor device, comprising:

a lower insulating layer on a substrate;

a conductive pattern in the lower insulating layer;

a middle insulating layer on the lower insulating layer and the conductive pattern;

a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer;

an upper insulating layer on the middle insulating layer and the via control region; and

a via plug passing through the via control region and connected to the conductive pattern.

2. The semiconductor device as claimed in claim 1, wherein top surfaces of the via control region and the middle insulating layer are substantially coplanar.

3. The semiconductor device as claimed in claim 1, wherein:

the middle insulating layer includes a low-k dielectric material; and

the via control region has a lower porosity than the middle insulating layer.

4. The semiconductor device as claimed in claim 1, wherein:

the middle insulating layer includes a SiO_XC_VH layer; and

the via control region includes a SiO_mC_nH layer,

wherein x>

0, y>

0, m>

0, n≥

0, x<

m, and y>

n.

5. The semiconductor device as claimed in claim 1, wherein a bottom surface of the via control region is at a higher level than a bottom surface of the middle insulating layer.

6. The semiconductor device as claimed in claim 5, wherein the bottom surface of the via control region is in contact with the middle insulating layer.

7. The semiconductor device as claimed in claim 1, wherein bottom surfaces of the via control region and the middle insulating layer are substantially coplanar.

8. The semiconductor device as claimed in claim 1, wherein:

a top surface of the lower insulating layer is at a lower level than a top end of the conductive pattern; and

a bottom end of the middle insulating layer is at a lower level than the top end of the conductive pattern.

9. The semiconductor device as claimed in claim 1, further comprising a glue layer between the lower insulating layer and the middle insulating layer, wherein:

the via plug passes through the glue layer;

the middle insulating layer includes a SiO_cC_yH layer; and

the glue layer includes a SiO_mC_nH layer,

wherein x>

0, y>

0, m>

0, n≥

0, x<

m, and y>

n.

10. The semiconductor device as claimed in claim 9, wherein the middle insulating layer is interposed between the via control region and the glue layer.

11. The semiconductor device as claimed in claim 9, wherein a side surface of the via plug is in contact with the via control region, the middle insulating layer, and the glue layer.

12. The semiconductor device as claimed in claim 9, wherein a bottom surface of the via control region is in contact with the glue layer.

13. The semiconductor device as claimed in claim 12, wherein a side surface of the via plug is in contact with the via control region and the glue layer.

14. The semiconductor device as claimed in claim 9, wherein the glue layer is thinner than the middle insulating layer.

15. The semiconductor device as claimed in claim 9, wherein the via control region is thicker than the glue layer.

16. The semiconductor device as claimed in claim 9, further comprising an etch stop layer between the lower insulating layer and the glue layer, the etch stop layer having an etch selectivity with respect to the middle insulating layer and the glue layer.

17. The semiconductor device as claimed in claim 16, wherein a side surface of the via plug is in contact with the via control region, the middle insulating layer, the glue layer, and the etch stop layer.

18. A semiconductor device, comprising:

a lower insulating layer on a substrate;

a plurality of conductive patterns in the lower insulating layer;

a middle insulating layer on the lower insulating layer and the conductive patterns;

a plurality of via control regions in the middle insulating layer, the via control regions being arranged between the plurality of conductive patterns, and the via control regions having a lower porosity than the middle insulating layer;

an upper insulating layer on the middle insulating layer and the via control regions; and

a via plug between the via control regions and connected to one selected from among the conductive patterns.

19. A semiconductor device, comprising:

a lower insulating layer on a substrate;

a conductive pattern in the lower insulating layer;

a middle insulating layer on the lower insulating layer and the conductive pattern;

a via control region formed in the middle insulating layer, the via control region including a material having a lower etch rate than the middle insulating layer;

an upper insulating layer on the middle insulating layer and the via control region;

a via plug passing through the via control region and connected to the conductive pattern; and

an upper interconnection in the upper insulating layer and connected to the via plug.

20. The semiconductor device as claimed in claim 19, wherein a top surface of the via control region is in contact with the upper interconnection.