Three-dimensional vertical NOR Flash Thin-Film Transistor Strings

• US 20190244971A1
• Filed: 01/18/2019
• Published: 08/08/2019
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Granted Patent: US 10,381,378 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operation;

a plurality of active columns of semiconducting material formed above the semiconductor substrate, each active column extending along a first direction orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped regions, wherein the active columns are arranged in a two-dimensional array having rows of active columns extending along a second direction and rows of active columns extending along a third direction, the second direction and the third direction each being parallel to the planar surface of the semiconductor substrate;

charge-trapping material provided over one or more surfaces of each active columns; and

a plurality of word line conductors that are electrically isolated from each other provided between the active columns in a plurality of stacks, each stack extending lengthwise along the third direction, wherein the active columns, the charge-trapping material and the word line conductors together form a plurality of variable-threshold thin-film transistors, each variable-threshold thin-film transistor comprising an associated one of the word line conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the word line conductor, and the first and second heavily doped regions;

first and second pluralities of interconnection conductors running lengthwise along the second direction above and beneath the active columns, respectively, wherein (i) the first heavily doped region forms a local bit line and serves as a first drain or source terminal of the variable-threshold thin-film transistor, the local bit line being selectably connected to an associated one of the second plurality of interconnection conductors, (ii) the associated word line conductor serves as a gate terminal to provide a control voltage to the variable-threshold thin-film transistor; and

(iii) the second heavily doped region forms a local source line and serves as a second drain or source terminal of the variable-threshold thin-film transistor, the local source line being connected to an associated one of the first plurality of interconnection conductors.

2. The memory structure of claim 1, wherein the second pluralities of interconnection conductors comprise a plurality of bit line segments beneath each row of active columns along the second direction, wherein the bit line segments are selectably electrically isolated from each other and each connect a predetermined number of local bit lines in the row of active columns.

3. The memory structure of claim 2, further comprising a plurality of regional bit line segments, wherein a plurality of bit line segments are selectably connected to each regional bit line segment.

4. The memory structure of claim 2, further comprising a plurality of segment-select transistors each selectably connecting a corresponding bit line segment to the circuitry in the semiconductor substrate.

5. The memory structure of claim 4, wherein the circuitry in the semiconductor substrate comprises at least a plurality of sense amplifiers distributed throughout the planar surface of the semiconductor substrate, the sense amplifiers being each connected by a different group of one or more segment-select transistors to corresponding bit line segments.

6. The memory structure of claim 4, wherein the segment-select transistors are formed in the semiconductor substrate.

7. The memory structure of claim 2, wherein each word line conductor provides gate terminals for variable-threshold thin-film transistors in active columns on opposite sides of the word line conductor, and wherein the local bit lines in adjacent active columns on opposite side of the word conductor are associated with different bit line segments.

8. The memory structure of claim 1, wherein the first pluralities of interconnection conductors comprise a plurality of source line segments above each row of active columns along the second direction, wherein the source line segments each connect a predetermined number of local source lines in the row of active columns.

9. The memory structure of claim 8, wherein the source line segments are selectably electrically isolated from each other.

10. The memory structure of claim 9, further comprising a global source line and a plurality of segment-select transistors, each segment-select transistor connecting a predetermined number of source line segments to the global source line.

11. The memory structure of claim 10, further comprising in each active column a pre-charge transistor for electrically connecting the local source line of the active column to the local bit line of the active column.

12. The memory structure of claim 11, wherein the local source lines connected by each source line segment provide a capacitance that serves as a virtual voltage source during a read, programming, program-inhibit or erase operation on one or more variable-threshold thin-film transistors in the active columns associated with the source line segment.

13. The memory structure of claim 8, further comprising a body bias voltage source in the semiconductor substrate, wherein the lightly doped region of each active column is connected to the body bias voltage source by a conductor above or below the active column.

14. The memory structure of claim 13, wherein the conductor above the active column comprises one of the first plurality of interconnection conductors.

15. The memory structure of claim 13, wherein the conductor above the active column is routed along the third direction.

16. The memory structure of claim 8 further comprising a plurality of charging columns each being associated with one of the source line segments, each charging column having first and second heavily doped regions structurally substantially the same as the first and second heavily doped regions of one of the active columns, wherein each charging column further comprises a plurality of pass transistors each selectably connecting the first and second heavily doped regions of the charging column, wherein at least one of the first and second heavily doped regions is connected to the circuitry in the semiconductor substrate.

17. The memory structure of claim 16, wherein each charging column is formed between two neighboring source line segments.

18. The memory structure of claim 16, wherein one or more of the word line conductors activate one or more of the pass transistors in one or more of the charge columns.

19. The memory structure of claim 18, further comprising a global source line that connects one or more of the word lines that activate one or more of the pass transistors in the one or more charge columns.

20. The memory structure of claim 16, wherein each charging column is connected to a voltage source in the semiconductor substrate by a segment-select transistor in the semiconductor substrate.

21. The memory structure of claim 20, wherein the voltage source supplies an erase voltage for a source line during an erase operation.

22. The memory structure of claim 1, wherein the active columns are isolated from each other by an isolation dielectric material or by an air gap.

23. The memory structure of claim 1, wherein the word line conductors in a stack are insulated from each other by an isolation dielectric material or air gap.

24. The memory structure of claim 1, wherein the variable-threshold thin-film transistors associated with each active column are organized in parallel into one or more NOR thin-film transistor strings.

25. The memory structure of claim 1, wherein the word line conductors in each stack at different positions along the first direction form steps of a stair-case structure and wherein each word line conductor is connected at the stair-case structure by vias to a corresponding one of the first or second pluralities of interconnection conductors.

26. The memory structure of claim 25, wherein selected word line conductors at selected steps of the stair-case structures in different stacks are connected to a selected one of the first or second pluralities of interconnection conductors.

27. A memory structure comprising first and second modular memory structures provided one on top of the other, wherein each modular memory structure comprises the memory structure of claim 25.

28. The memory structure of claim 27, wherein the first and second modular memory structures are isolated from each other by a dielectric layer.

29. The memory structure of claim 28, wherein active columns in the first and second modular memory structures are aligned along the first direction and wherein in local source lines of corresponding active columns are connected by vias through the dielectric layer.

30. The memory structure of claim 1, further comprising metallic pylons embedded in either one or both of the local source line and the local bit line of one or more active columns,

31. The memory structure of claim 30, wherein the metallic pylons each comprises one or more of titanium nitride, tungsten nitride or tungsten.

32. The memory structure of claim 31, wherein the metallic pylon is formed using an atomic layer deposition technique.

33. The memory structure of claim 1, wherein the lightly doped region in each active column comprises a first section and a second section, and wherein the first section of the lightly doped region serves as channel regions for the variable-threshold thin-film transistors of the active columns and wherein the second section of the lightly doped region has a dopant concentration multiple times that of the first section of the lightly doped region.