Buffer Amplifier

• US 20190245524A1
• Filed: 02/07/2019
• Published: 08/08/2019
• Est. Priority Date: 02/08/2018
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: DB HiTek Co., Ltd.
• Inventors: KIM, Ik-Hyun
• Granted Patent: US 10,630,266 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A buffer amplifier configured to perform voltage switching (DC bias voltage switching). The buffer amplifier includes first and second amplification blocks corresponding to first and second channels, respectively, first and second output buffer units controlled by output levels of the first and second amplification blocks, and a switch unit configured to connect or disconnect the first or second amplification block to or from the first or second output buffer unit. The switch unit includes a first switch unit configured to connect or disconnect one of the first and second amplification blocks to or from the first output buffer unit based on or in response to a control signal and a second switch unit configured to connect or disconnect another one of the first and second amplification blocks to or from the second output buffer unit based on or in response to the control signal.

Claims

1. A buffer amplifier comprising:

a first amplification block;

a second amplification block;

a first output buffer unit receiving an output level of the first amplification block;

a second output buffer unit receiving an output level of the second amplification block; and

a switch unit configured to connect or disconnect the first amplification block or the second amplification block to or from the first output buffer unit or the second output buffer unit,

wherein the switch unit includes a first switch unit configured to connect one of the first amplification block and the second amplification block to the first output buffer unit based on or in response to a control signal; and

a second switch unit configured to connect a different one of the first amplification block and the second amplification block to the second output buffer unit based on or in response to the control signal.

2. The buffer amplifier according to claim 1, wherein each of the first amplification block and the second amplification block comprises:

an input unit configured to amplify a first input signal and output first through fourth currents; and

an amplifier unit including a first current mirror, a second current mirror, and a biasing unit connected between the first current mirror and the second current mirror, wherein the first current mirror includes (i) a first PMOS transistor and a second PMOS transistor connected in series at a first node configured to receive the first current and (ii) a third PMOS transistor and a fourth PMOS transistor connected in series at a second node configured to receive the second current, and the second current mirror includes (i) a first NMOS transistor and a second NMOS transistor connected in series at a third node configured to receive the third current, and (ii) a third NMOS transistor and a fourth NMOS transistor connected in series at a fourth node configured to receive the fourth current.

3. The buffer amplifier according to claim 2, wherein the switch unit is configured to connect one of the first output buffer unit and the second output buffer unit to the amplifier unit.

4. The buffer amplifier according to claim 2, wherein the biasing unit comprises:

a first bias circuit connected between the second PMOS transistor of the first current mirror and the second NMOS transistor of the second current mirror; and

a second bias circuit connected between the fourth PMOS transistor of the first current mirror and the fourth NMOS transistor of the second current mirror.

5. The buffer amplifier according to claim 2, wherein each of the first current mirror and the second current mirror comprises a cascode current mirror.

6. The buffer amplifier according to claim 4, wherein each of the first bias circuit and the second bias circuit includes an N-type transistor and a P-type transistor that are connected in parallel, and each of the N-type transistor and the P-type transistor have a gate configured to receive a bias voltage.

7. The buffer amplifier according to claim 1, wherein:

each of the first output buffer and the second output buffer includes an N-type transistor and a P-type transistor that are connected in series,

the first buffer unit has a first terminal configured to receive a first power supply voltage and a second terminal configured to receive a second power supply voltage,

the second output buffer has a first terminal configured to receive a first power supply voltage and a second terminal configured to receive the second power supply voltage,

the first power supply voltage is higher than the second power supply voltage, and

the third power supply voltage is lower than the second power supply voltage.

8. The buffer amplifier according to claim 1, wherein each the first input unit and the second input unit is configured to receive feedback from corresponding one of the first output buffer unit and the second output buffer unit.

9. The buffer amplifier according to claim 1, wherein the first switch unit comprises:

a first switch configured to connect or disconnect a first output node of the first amplification block to or from a P-type transistor of the first output buffer unit based on or in response to the control signal;

a second switch configured to connect or disconnect a first output node of the second amplification block to or from the P-type transistor of the first output buffer unit based on or in response to the control signal;

a third switch configured to connect or disconnect a second output node of the first amplification block to or from an N-type transistor of the first output buffer unit based on or in response to the control signal; and

a fourth switch configured to connect or disconnect a second output node of the second amplification block to or from the N-type transistor of the first output buffer unit based on or in response to the control signal.

10. The buffer amplifier according to claim 1, wherein the second switch unit comprises:

a fifth switch configured to connect or disconnect a first output node of the first amplification block to or from a P-type transistor of the second output buffer unit based on or in response to the control signal;

a sixth switch configured to connect or disconnect a first output node of the second amplification block to or from the P-type transistor of the second output buffer unit based on or in response to the control signal;

a seventh switch configured to connect or disconnect a second output node of the first amplification block to or from an N-type transistor of the second output buffer unit based on or in response to the control signal; and

an eighth switch configured to connect or disconnect a second output node of the second amplification block to or from the N-type transistor of the second output buffer unit based on or in response to the control signal.

11. A buffer amplifier comprising:

a first amplification block;

a second amplification block;

a first output buffer unit configured to receive an output level of the first amplification block;

a second output buffer unit configured to receive an output level of the second amplification block; and

a switch unit configured to connect or disconnected the first amplification block or the second amplification block to or from the first output buffer unit or the second output buffer unit,

wherein each of the first amplification block and the second amplification block comprises;

an input unit configured to differentially amplify a first input signal to generate a differential current; and

an amplifier unit configured to output a control signal based on or in response to the differential current,

the switch unit comprises;

a first switch subunit configured to connect one of the first amplification block and the second amplification block to the first output buffer unit based on or in response to the control signal; and

a second switch subunit configured to connect a different one of the first amplification block and the second amplification block to the second output buffer unit based on or in response to the control signal.

12. The buffer amplifier according to claim 11, wherein the input unit comprises a first differential amplifier including:

a first NMOS transistor connected to one of first and second nodes of the amplifier unit and configured to receive the first input signal at a gate thereof;

a second NMOS transistor connected to a remaining one of the first node and the second node of the amplifier unit and configured to receive a second input signal at a gate thereof; and

a first bias unit connected to a second rail that supplies a first power supply voltage and configured to control a bias current to the first NMOS transistor and the second NMOS transistor based on or in response to a first complementary bias voltage.

13. The buffer amplifier according to claim 12, wherein the input unit further comprises a second differential amplifier including:

a first PMOS transistor connected to one of third and fourth nodes of the amplifier unit and configured to receive the first input signal at a gate thereof;

a second PMOS transistor connected to a remaining one of the third node and the fourth node of the amplifier unit and configured to receive the second input signal at a gate thereof; and

a second bias unit connected to a first rail that supplies a second power supply voltage and configured to control a bias current to the first PMOS transistor and the second PMOS transistor based on or in response to a second complementary bias voltage.

14. The buffer amplifier according to claim 13, wherein the input unit generates a first current, a second current, a third current, and a fourth current,

the first current flows between a drain of the first NMOS transistor and the first node,

the second current flows between a drain of the second NMOS transistor and the second node,

the third current flows between a drain of the first PMOS transistor and the third node, and

the first current flows between a drain of the second PMOS transistor and the fourth node.

15. The buffer amplifier according to claim 14, wherein the amplifier unit comprises a first current mirror configured to control a voltage at a first output node to the output buffer unit based on or in response to at least one of the first current, the second current, and a first bias voltage, wherein the first current mirror comprises:

a third PMOS transistor and a fourth PMOS transistor connected in series at the first node; and

a fifth PMOS transistor and a sixth PMOS transistor connected in series at the second node.

16. The buffer amplifier according to claim 15, wherein the amplifier unit further comprises a second current mirror configured to control a voltage at a second output node to the output buffer unit based on or in response to at least one of the third current, the fourth current, and a second complementary bias voltage,

wherein the second current mirror comprises:

a third NMOS transistor and a fourth NMOS transistor connected in series at the third node; and

a fifth NMOS transistor and a sixth NMOS transistor connected in series at the fourth node.

17. The buffer amplifier according to claim 16, wherein the amplifier unit further comprises a third bias unit connected between the first current mirror and the second current mirror,

wherein third bias unit comprises:

a seventh PMOS transistor configured to receive a third bias voltage through a gate thereof; and

a seventh NMOS transistor configured to receive a complementary bias voltage through a gate thereof, and

the seventh PMOS transistor and the seventh NMOS transistor are connected in parallel, and a source and a drain of the seventh PMOS transistor and a source and a drain of the seventh NMOS transistor are connected between a first intermediate node and a second intermediate node.

18. The buffer amplifier according to claim 17, wherein the amplifier unit further comprises a fourth bias unit connected between the first current mirror and the second current mirror, the fourth bias unit including a first floating bias and a second floating bias.

19. The buffer amplifier according to claim 11, wherein each of the first output buffer unit and the second output buffer unit includes an N-type transistor and a P-type transistor that are connected in series,

the first buffer unit has a first terminal configured to receive a first power supply voltage and a second terminal configured to receive a second power supply voltage, the second output buffer has a first terminal configured to receive a third power supply voltage and a second terminal configured to receive the third power supply voltage, the first power supply voltage is higher than the second power supply voltage, and the third power supply voltage is lower than the second power supply voltage.