Buffer Amplifier
First Claim
1. A buffer amplifier comprising:
- a first amplification block;
a second amplification block;
a first output buffer unit receiving an output level of the first amplification block;
a second output buffer unit receiving an output level of the second amplification block; and
a switch unit configured to connect or disconnect the first amplification block or the second amplification block to or from the first output buffer unit or the second output buffer unit,wherein the switch unit includes a first switch unit configured to connect one of the first amplification block and the second amplification block to the first output buffer unit based on or in response to a control signal; and
a second switch unit configured to connect a different one of the first amplification block and the second amplification block to the second output buffer unit based on or in response to the control signal.
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Accused Products
Abstract
A buffer amplifier configured to perform voltage switching (DC bias voltage switching). The buffer amplifier includes first and second amplification blocks corresponding to first and second channels, respectively, first and second output buffer units controlled by output levels of the first and second amplification blocks, and a switch unit configured to connect or disconnect the first or second amplification block to or from the first or second output buffer unit. The switch unit includes a first switch unit configured to connect or disconnect one of the first and second amplification blocks to or from the first output buffer unit based on or in response to a control signal and a second switch unit configured to connect or disconnect another one of the first and second amplification blocks to or from the second output buffer unit based on or in response to the control signal.
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Citations
19 Claims
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1. A buffer amplifier comprising:
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a first amplification block; a second amplification block; a first output buffer unit receiving an output level of the first amplification block; a second output buffer unit receiving an output level of the second amplification block; and a switch unit configured to connect or disconnect the first amplification block or the second amplification block to or from the first output buffer unit or the second output buffer unit, wherein the switch unit includes a first switch unit configured to connect one of the first amplification block and the second amplification block to the first output buffer unit based on or in response to a control signal; and
a second switch unit configured to connect a different one of the first amplification block and the second amplification block to the second output buffer unit based on or in response to the control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A buffer amplifier comprising:
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a first amplification block; a second amplification block; a first output buffer unit configured to receive an output level of the first amplification block; a second output buffer unit configured to receive an output level of the second amplification block; and a switch unit configured to connect or disconnected the first amplification block or the second amplification block to or from the first output buffer unit or the second output buffer unit, wherein each of the first amplification block and the second amplification block comprises; an input unit configured to differentially amplify a first input signal to generate a differential current; and an amplifier unit configured to output a control signal based on or in response to the differential current, the switch unit comprises; a first switch subunit configured to connect one of the first amplification block and the second amplification block to the first output buffer unit based on or in response to the control signal; and a second switch subunit configured to connect a different one of the first amplification block and the second amplification block to the second output buffer unit based on or in response to the control signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification