BINARY NEURAL NETWORK ACCELERATOR ENGINE METHODS AND SYSTEMS

• US 20190251425A1
• Filed: 02/15/2019
• Published: 08/15/2019
• Est. Priority Date: 02/15/2018
• Status: Active Grant

• Current Assignee: Nordic Semiconductor ASA
• Original Assignee: Atlazo, Inc.
• Inventors: Jaffari, Javid, Arabi, Karim, Beraha, Rodolfo
• Granted Patent: US 11,488,002 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 7/575 Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/048 Activation functions
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 5/01 Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
• CPC Class Codes: G06V 10/764 using classification, e.g. of video objects
• CPC Class Codes: G06V 10/82 using neural networks
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding

Abstract

Disclosed are methods, apparatus and systems for a binary neural network accelerator engine. One example circuit is designed to perform a multiply-and-accumulate (MAC) operation using logic circuits that include a first set of exclusive nor (XNOR) gates to generate a product vector based on a bit-wise XNOR operation two vectors. The result is folded and operated on by another set of logic circuits that provide an output for a series of adder circuits. The MAC circuit can be implemented as part of binary neural network at a small footprint to effect power and cost savings.

Claims

1. A logic circuit for computing a dot product in a binary neural network, the logic circuit comprising:

a first set of exclusive nor (XNOR) gates, each XNOR gate configured to receive one bit of a first vector of length N bits and one bit of a second vector of length N bits, to generate a product vector of length N bits at the output of the first set of XNOR gates;

a first buffer and a second buffer each having a length N/2 bits to store the product vector in two portions, each of the first and the second buffers coupled to inputs of a second set of XNOR gates and to inputs of a first set of NOR gates;

a third buffer and a fourth buffer each having a length N/2 bits, wherein the third buffer is configured to store output results of the first set of NOR gates, and the fourth buffer is configured to store output results of the second set of XNOR gates; and

a plurality of adders having inputs that are coupled to the third and the fourth buffers and configured to add binary values stored in the third and the fourth buffers to generate the dot product of the first and second bit vectors.

2. The logic circuit of claim 1, wherein the plurality of adders are arranged in a tree structure having multiple levels, each level having a plurality of logic gates, wherein the binary values stored in the third and the fourth buffers are input to a first level of the tree structure, and outputs of the first level are connected to inputs of a second level of the tree structure.

3. The logic circuit of claim 1, wherein the plurality of adders comprises N/4 2-bit adders and N/8 3-bit adders.

4. The logic circuit of claim 3, wherein the plurality of adders further comprises N/16 4-bit adders and N/32 5-bit adders.

5. The logic circuit of claim 4, wherein the plurality of adders further comprises N/64 6-bit adders and N/128 7-bit adders.

6. A circuit for implementing a binary neural network, comprising:

a plurality of convolutional layers configured to implement at least a dot product of two-bit vectors, each vector having length N, based on a logic circuit;

a plurality of pooling layers; and

a plurality of fully connected layers,

wherein a first layer of the plurality of convolutional layers is configured to receive an input signal, wherein a last layer of the plurality of fully connected layers is configured to provide a recognition value for the input signal in each of a plurality of classes, and wherein the logic circuit comprises;

a first set of logic gates configured to compute a bit-wise exclusive nor (XNOR) operation on the two bit vectors,

a second set of logic gates configured to perform at least two distinct binary operations on a folded output of the bit-wise XNOR operation, and

a third set of logic gates configured to add results of the at least two distinct binary operations.

7. The circuit of claim 6, wherein the input signal comprises an image, a temperature measurement, a humidity measurement, an electrocardiogram (EKG) reading, a heart rate or a hydration measurement.

8. The circuit of claim 6, wherein a first number of filters in the first layer of the plurality of convolutional layers is different from a second number of filters in a subsequent of layer of the plurality of convolutional layers.

9. The circuit of claim 6, further comprising:

one or more tightly coupled memory units that are partitioned into four segments,

wherein at least one of the four segments of the one or more tightly coupled memory units stores filter weights associated with the plurality of convolutional layers.

10. The circuit of claim 7, wherein the circuit is controlled using an instruction set comprising at least one instruction that moves data between a system memory and the one or more tightly coupled memory units.

11. The circuit of claim 6, wherein the at least two distinct binary operations comprise a bit-wise XNOR operation and a bit-wise NOR operation.

12. The circuit of claim 6, wherein the third set of logic gates comprises a plurality of adders that are arranged in a tree structure having multiple levels.

13. A logic circuit for computing a dot product in a binary neural network, the logic circuit comprising:

a first set of logic gates configured to receive two bit vectors and compute a first bit-wise exclusive nor (XNOR) operation on the two bit vectors;

a second set of logic gates configured to perform a second bit-wise XNOR operation and a bit-wise NOR operation on a folded output of the first bit-wise XNOR operation; and

a third set of logic gates configured to add results of the second bit-wise XNOR operation and the bit-wise NOR operation.

14. A neural network system for signal classification, comprising:

a first neural network comprising;

a first input to receive an input signal,

a second input to receive a wakeup signal,

a first processor to perform, upon receiving the wakeup signal, a first classification of the input signal to produce a first classification result, and

an output to provide the first classification result; and

a second neural network comprising;

an input to receive the input signal,

a second processor to continuously perform a second classification of the input signal to produce a second classification result, and

an output coupled to the second input of the first neural network to provide the wake-up signal based on the second classification result,

wherein;

the first neural network is configured to operate intermittently to remain in an off mode of operation and to only switch to an on mode of operation upon receiving the wake-up signal from the second neural network,

the second neural network is configured to continually process the input signal in an always-on mode of operation and to generate the wake-up signal upon a determination of the second classification result.

15. The neural network system of claim 14, wherein the first classification result is more accurate than the second classification result.

16. The neural network system of claim 14, wherein the second neural network is a binary neural network.

17. The neural network system of claim 16, wherein the binary neural network comprises a logic circuit for computing a dot product in a binary neural network, the logic circuit comprising:

a first set of logic gates configured to receive two bit vectors and compute a first bit-wise exclusive nor (XNOR) operation on the two bit vectors;

a second set of logic gates configured to perform a second bit-wise XNOR operation and a bit-wise NOR operation on a folded output of the first bit-wise XNOR operation; and

a third set of logic gates configured to add results of the second bit-wise XNOR operation and the bit-wise NOR operation.

18. The neural network architecture of claim 14, wherein the first neural network is a real-valued convolutional neural network.

19. The neural network architecture of claim 14, wherein the first neural network is a binary neural network, and wherein the first classification operates on more classes than the second classification.

20. The neural network architecture of claim 14, wherein the second neural network is configured to:

(a) process a limited subset of tasks compared to the first neural network, or (b) process the same set of tasks as the first neural network but at a lower precision or accuracy compare to the first neural network.