SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

• US 20190252382A1
• Filed: 04/25/2019
• Published: 08/15/2019
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: Schober, Susan Marya, Schober, Robert C.
• Granted Patent: US 10,446,547 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 2203/45246 the dif amp being biased in the subthreshold region
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/165 with junction-FET's
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel.The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.

Claims

1. A field effect transistor comprising:

a. a source diffusion connected to a source terminal;

b. a drain diffusion connected to a drain terminal;

c. a third diffusion connected to a bidirectional current terminal (iPort), interposed between the source and drain diffusions, defining a source channel segment between the source diffusion and the third diffusion, and a drain channel segment between the drain diffusion and the third diffusion;

d. a gate capacitively coupled with the source channel segment and the drain channel segment,

wherein

a ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.

2. The field effect transistor of claim 1, wherein a trans-resistance of the field effect transistor is established by a ratio of:

a. the ratio of the width and the length of the drain channel segment; and

b. the ratio of the width and the length of the source channel segment.

3. The field effect transistor of claim 2, wherein a current applied at the bidirectional current terminal is converted to a voltage by the trans-resistance.

4. A field effect transistor comprising:

a. a source diffusion connected to a source terminal;

b. a drain diffusion connected to a drain terminal;

c. an intermediate diffusion connected to an intermediate bidirectional current terminal (iPort), the intermediate diffusion interposed between the source and drain diffusions, and defining a source channel segment between the source diffusion and the intermediate diffusion, and a drain channel segment between the drain diffusion and the intermediate diffusion;

d. a first gate terminal capacitively coupled with the source channel segment; and

e. a second gate terminal capacitively coupled with the drain channel segment,

a ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.

5. The field effect transistor of claim 4, wherein a trans-resistance of the field effect transistor is established by a ratio of:

a. the ratio of the width and the length of the drain channel segment; and

b. the ratio of the width and the length of the source channel segment.

6. The field effect transistor of claim 5, wherein a current applied at the bidirectional current terminal is converted to a voltage by the trans-resistance.