SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE
1. A field effect transistor comprising:
- a. a source diffusion connected to a source terminal;
b. a drain diffusion connected to a drain terminal;
c. a third diffusion connected to a bidirectional current terminal (iPort), interposed between the source and drain diffusions, defining a source channel segment between the source diffusion and the third diffusion, and a drain channel segment between the drain diffusion and the third diffusion;
d. a gate capacitively coupled with the source channel segment and the drain channel segment,whereina ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.
The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel.The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.
- 1. A field effect transistor comprising:
a. a source diffusion connected to a source terminal; b. a drain diffusion connected to a drain terminal; c. a third diffusion connected to a bidirectional current terminal (iPort), interposed between the source and drain diffusions, defining a source channel segment between the source diffusion and the third diffusion, and a drain channel segment between the drain diffusion and the third diffusion; d. a gate capacitively coupled with the source channel segment and the drain channel segment, wherein a ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.
- View Dependent Claims (2, 3)
- 4. A field effect transistor comprising:
a. a source diffusion connected to a source terminal; b. a drain diffusion connected to a drain terminal; c. an intermediate diffusion connected to an intermediate bidirectional current terminal (iPort), the intermediate diffusion interposed between the source and drain diffusions, and defining a source channel segment between the source diffusion and the intermediate diffusion, and a drain channel segment between the drain diffusion and the intermediate diffusion; d. a first gate terminal capacitively coupled with the source channel segment; and e. a second gate terminal capacitively coupled with the drain channel segment,
- View Dependent Claims (5, 6)
The present application is a continuation of the non-provisional application Ser. No. 15/748,908, filed on Jan. 30, 2018, which is 35 U.S.C. § 371 National Phase Entry of, and claims priority to PCT International Application No. PCT/2016/044800 filed on Jul. 29, 2016, which claims the benefit of and priority to U.S. Provisional Application No. 62/267,174 filed on Dec. 14, 2015, the contents of which are incorporated herein by reference.
The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to super-saturation current field effect transistors.
The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or “IoT”). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore'"'"' s Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.
In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-μm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or “RF”) designers still struggle to discover how to make high-performance integrated circuits (or “ICs”) for ultra-deep sub-μm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium.
The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore'"'"'s law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (-18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These “mixed-mode” IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Reprobating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.
Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the “R” and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant “bias” currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.
As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not substantially change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving sufficient room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.
The conventional MOS amplifier gain formation is an input voltage driving a trans-conductance (gm) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high to provide the required voltage gain, these load transistors must be very long, but to drive enough current these transistors must be very wide also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drives is additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifiers output resistance, modifying the AC performance. What is actually needed is exactly the inverse operating principle, which the present invention is about.
The baseline comparisons are (all made in an 180 nm IC process) in the form of performance plots as in: a Bode Gain-Phase plot over frequency
Normally MOS amplifiers operate within a square-law relationship due to the strong inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the “moderate-inversion” transition between these two operating mode provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about amplifiers that operate in the exponential mode.
To understand the prior art, let'"'"'s begin with a discussion of Weak vs. Strong inversion. Referring to
- Drain to Source voltage is small (on the order of 100 mV);
- The gate G (or 17s) is at a similar small potential (typically less than 300 mV);
- This creates a surface conduction layer, of uniform depth from source S to drain D;
- The conductivity of this surface layer is exponential with respect to the Gate G voltage;
- This allows operation over many decades (about 6) of dynamic range;
- The channel appears as a moderate value resistor (100+s of K-Ohms); and
- The uniform depth conduction channel promotes an exponentially higher gain but with a speed penalty (due to low charge density in the conduction channel).
Strong inversion (referring to
- Drain to Source voltage is larger than the Gate to Source voltage Vg of
FIG. 1gand threshold Vthreshold in FIG. 1h(typically in excess of 400 mV);
- The Gate 17u is operated above its threshold voltage Vthreshold;
- This creates a conduction channel that is deeper at the Source and tapers to near pinch-off at the Drain 12u;
- The resulting conduction layer behaves with a Square-law response to the gate voltage at the Gate 17u;
- Dynamic range is limited to about 3 decades as compared to weak inversion;
- The channel 12g appears as an adjustable current source (high value resistor); and
- The wedge shape of the conduction channel 12g provides higher speed than weak inversion because of higher charge density in the conduction channel.
- Drain to Source voltage is larger than the Gate to Source voltage Vg of
Now, referring back to
A 3-dimensional prospective view of this MOS transistor structure is shown in
Although similar MOS structures appear in prior art, no significant exploitation of many of its unique properties are known or published. In addition, proper biasing remains as a problem(s) for its operation(s). A deeper understanding of the internal mechanisms resulted in discovery of many desirable applications (enabling superior operation at deep-sub-micron scale), including an approach to proper biasing that takes advantage of natural equilibrium. This natural equilibrium is the result of a “Band-Gap” voltage reference mechanism, again functional at deep-sub-micron scale.
Although a cascade amplifier can be found in prior art, the prior art does not contain a complementary pair of cascade transistors connected as a totem-pole. With this simple compound structure, feedback from the output to the input can be used to self-bias the resulting inverter into its linear mode. As mentioned above, biasing of an amplifier has always been problematic; however, the novel and inventive self-biasing structure of the present invention addresses such an issue. Advantages of the configuration of the present invention (referred to as a complementary iFET or CiFET) are many, including, but not limited to:
- Gain of the single stage is maximum when the output is at the midpoint (self-bias point);
- The gain of a single CiFET stage is high (approaching 100), therefore, while the final output may swing close to the rails, its input remains near the midpoint. The stage before that, because of the high gain, operates its input and output near the mid-point (“sweet-spot”) where the gain is maximized. So too for each of the preceding stages;
- Slew rate and symmetry are maximized where the channel current is highest (near the mid-point);
- Noise is minimized where the channel current is highest (near the mid-point); and
- Parasitic effects are negligible where the voltage swing is small.
When the gate input signal moves in one direction, the output moves in the inverse direction. For example; a positive input yields a negative output, not so much because the N-channel device is turned on harder, but rather because the P-channel device is being turned off. Thevenin/Norton analysis shows that the current through the P and N devices must be exactly the same, because there is nowhere else for drain current in one transistor to go except through the drain of the complementary transistor; however, the voltage drop across those devices does not have to be equal, but must sum to the power supply voltage. Due to the super-saturated source channel, these voltages are tied together exponentially. This is even more evident at low power supply voltages where the voltage gain peaks. This means that the gate-to-source voltage is precisely defined by the same and only drain current going through both transistors. Exponentials have the unique physical property like a time constant, or “half-life;” It does not matter where we are at a given point of time, a time constant later we will be a fixed percentage closer to the final value. This is a “minds-eye” illustration of the primary contributor to output movement in response to input change. This same current balance of gate-to-source operating voltages also indicates why the “sweet-spot” in the self-biased amplifier is so repeatable. In effect it is used as a differential pair-like reference point to the amplifier input signal.
It is to be noted that during the transition from vacuum tubes to bipolar transistors the industry underwent a major paradigm shift, learning to think in terms of current rather than voltage. With the advent of FETs & MOSFETs the pendulum swing is back toward thinking in terms of voltage, but much knowledge has been lost or forgotten. Herein is contained the rediscovery of some old ideas as well as some new ones, all applied to the up-coming “current” state of the art. It is believed that the inherent simplicity of the present invention speaks to their applicability and completeness.
A first issue may be that there is always a need for a little analog functionality, yet nearly all analog performance metrics of a MOS transistor are remarkably poor as compared to that of a Bipolar transistor. The industry has made MOS devices serve by employing extensive “work-arounds.” Conventional analog design is constrained by one or more of the followings:
- Power supply voltages sufficient to bias the stacked thresholds, and transistors large enough to supply the necessary output drive current while still providing the high output impedance required for linearity and gain (gm*RL).
- Lack of analog IC process extensions (unavailable at nanometer scale) are required for linear signals, let alone with the enhanced performance demonstrated herein.
- Resistors, inductors, and large capacitors are mostly non-existent for analog designs in newer IC processes.
In contrast, bipolar transistors can be made to have high gain (β), wider bandwidth, wider dynamic range (many decades, from near the rails down to the noise floor), better matching (found in differential pairs), and band-gap references. Junction FETs, which operate with sub-surface channel conduction below the surface defects, have lower noise than bipolar transistors. Likewise the CiFET super-saturated source channel operates primarily below the defects at the channel surface underneath the gate oxide.
MOS designs are poorer in the above areas but have their own extreme advantages, including, but not limited to:
- MOS devices are small and relatively simple
- highly scalable
- high speed
- low power
- ultra-dense/high functionality systems on a chip, where Bipolar designs cannot go (deep sub-μm scale).
Accordingly, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.
Today the real-world of analog circuit design, signals still need to be converted on both the front and back end of signal processing systems. This need has become a road-block at deep sub-um scale.
Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage inverter, with a closed loop, is stable (does not oscillate). Increased loop gain requires stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate—because they are ring oscillators).
The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep-sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.
There is a long felt need for low-cost/high-performance systems integrated on a single chip for affordable high-volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices.
The present invention relates to circuits built out of a novel and inventive compound device structure, which enables a charge-based approach that takes advantage of exponential relationships of a super-saturated source channel below which possesses sub-threshold-like operation when used for analog CMOS circuit designs. The present invention is an evolution of an ordinary CMOS inverter, and further improvement of a current field effect transistor (iFET). It provides extremely high precision, speed, linearity, low noise, and a compact physical layout, using an all-digital nanoscale or deep sub-μm IC process. In addition to the expected digital inverter function, five classes of analog circuits are exemplified: a voltage input amplifier, a current input amplifier, a current inverter as opposed to a current mirror, an adjustable delay circuit, and a voltage or current reference source. Take special note that analog functionality is realized, in a digital IC process, using a single optimized digital logic circuit cell.
According to another aspect of the present invention, it provides a super-saturation iFET (or xiFET) device having a source terminal, a drain terminal and a diffusion (or iPort) terminal, defining a source channel between the source terminal and diffusion terminal, and a drain channel between the drain terminal and the diffusion terminal. Instead of a common gate that capacitively coupled to the source and drain channels, the device has a first gate that is capacitively coupled to the source channel and a second gate that is capacitively coupled to the drain channel.
According to another aspect of the present invention, it takes advantage of the Doping Profile and Ratioing. Not everything in optimizing a circuit has to do with the circuits'"'"' electrical configuration. Proper device sizing and especially adjusting the size relationship between complementary transistors provides considerable performance benefits. The xiFET, being a compound structure, offers extensive opportunity to establish impedance matching and gain control through proper ratio of the physical device parameters. Other important characteristics, like noise, speed, and power, can be tailored through careful specification of the physical construction and doping of the transistors, rather than relying solely on circuit configuration.
According to yet another aspect of the present invention, it provides certain noise advantages. In the end, it comes down to signal-to-noise ratio. Low power supply voltage requirements in ultra-deep-sub-micron IC processes limit the maximum signal swing to a much smaller number than most analog designers are used to. So with a smaller signal, the low-noise techniques embodied herein must be employed in order to maintain the desired signal to noise ratio.
Additional Advantages may be provided by the present invention. The primary advantage delivered by this technology is the ability to produce analog building blocks constructed entirely from digital parts, without analog extensions. Equally important is the fact that it actually operates at ultra-deep-sub-micron scale, and operates best at reduced power supply voltages below one volt as required for ultra-deep sub-p.m IC processes. These three factors contribute to an unprecedented portability of designs across process nodes. Entirely new circuit designs will be realized because of a FET that has more than one control input. The CiFET offers a high-impedance voltage control on the gate while simultaneously offering a low-impedance current control at the iPorts. These two inputs operate independently of each other and their independent response is summed at the output.
According to yet another aspect of the present invention, it provides a complementary xiFET compound device, which can be configured as a current input amplifier or complementary current low noise amplifier (CxiLNA). For example, the CxiFET compound device, used as a current amplifier, offers an unexpectedly wider dynamic range with great linearity over an extreme frequency range. This CxiLNA provides constant gain and input resistance in its passband. The CxiLNA of the present invention does not suffer from phase shift in the passband. This CxiLNA operates with power supplies down to the millivolt level with a reasonable bandwidth. The CxiLNA is not dependent on operation above the normal MOS threshold voltages. A skilled reader in the art would appreciate and find it useful in many applications as a gain block that is unencumbered by the surrounding parasitics, due to the fact that CxiLNA of the present invention exhibits an incredibly higher signal to noise ratio. Such a performance is seldom seen, even in LNAs.
A MOS structure referred to herein as an iFET, where the letter “i” refers to a current and “FET” refers to a Field Effect Transistor, is the enabling element of several high performance and novel designs of the present invention. The present invention is based on the addition of a direct connection to a mid-point in a Field Effect Transistor (or FET) channel and the realization that this is a low impedance port (current port, or herein referred to as “iPort”) providing a bidirectional current sink/source mid-channel with a very low input impedance at a low saturation voltage, and additionally connecting reciprocal iFETs pairs of opposite “conductivity type” (P-type & N-type) interconnected to take advantage of their complementary nature to operate as a team and symmetry to self-bias near the midpoint between power supplies. In addition, the relative strength of the first and second channels of the iFETs can be adjusted (threshold choice, relative sizing, and doping profiles) to tailor the gain, speed, quiescent current and input impedance of such a complementary iFET (or CiFET) compound device of the present invention.
The iFET, with its iPort provides an uncommon and unexpected solution to the compensation problem, and then continues to provide new or alternative solutions to other old problems, exceeding industry expectations. The advantages of operating circuits in “weak inversion” have long been known but, so also have the problems. The CiFET enables circuits to exploit the high gain and wider dynamic range available in “weak inversion,” without sacrificing superior speed performance. The CiFET compound device provides a standard active IC gain device that is superior to ordinary analog MOSETs making digital ICs host analog functionality. It is not a tradeoff.
The following is a list of some of the unusual aspects of a CiFET based circuit, including, but not limited to:
- Operates at low power supply voltage;
- High gain;
- Extremely linear;
- Very high speed (wide band);
- Low noise;
- Quick recovery (DC);
- Uses all digital parts and processes;
- iPorts respond to charge (things in nature are charge based) rather than Volts across a Resistance; and
- iPort has wide dynamic range with constant gain in an open loop.
The gate control terminal 27a or 27b operates like a conventional MOSFET insulated gate, with its high input impedance and a characteristic Trans-conductance (gm) transfer function. Typical values of (gm) for a small-signal MOSFET transistor are 1 to 30 millisiemens (1 millisiemen=1/1 K-ohm) each, a measure of Trans-conductance.
The iPort control terminal 21a or 21b is low impedance with respect to the source terminal 24a or 24b, and has a transfer function that looks more like beta (β) of a bipolar transistor, but is actually Trans-resistance (or rm), or more generally, especially at high frequencies, Trans-impedance, measured in K-ohms, where the output voltage is a consequence of an input current. Depending on the channel sizing ratio of the CiFET the typical resistance values (or values of rm) for a small-signal iFET transistor 200 are from 1 KΩ to 4 MΩ, a measure of Trans-resistance. Current input to voltage output (Trans-impedance) is the basis for the assertion that 1 μA in will yield an output of 100 mV (or a gain of 100,000:1) at a large signal level, or 1 pA in will yield an output of 100 nanoV (or a gain of 100,000:1) in a low noise amplifier (or LNA) (both results from the same circuit and linear over this dynamic range).
These values have been shown to remain true for a single minimum sized iFET, with inputs from 1 pico-ampere to 10 micro-amperes, using the same circuit in simulation. In 180 nm CMOS construction the noise floor limits measurements below about 10 pico-amps. iFETS can be constructed with different length to width proportions with very predictably differing results.
High gain, uncharacteristic or surprising results differing from the state of the art designs, is the result of the “Weak inversion” characteristics of the source channel 23b of the iFET 200 operating in a highly ionized super-saturation mode of
Speed in this super-saturated source channel 23b is not limited by the transit time of carriers along the channel 23b, but the high concentration of ionized charge carriers in the active channel only have to push the surrounding charge a little as charge is either added or removed from the channel 23b by means of the iPort control terminal 21b, resulting in a diffusion current which is defined by exponential relationship as has been realized when a MOSFET is operated in weak-inversion. This is in contrast to an electric field causing the charge to transit the channel, which is a square-law function of the gate control voltage. In this configuration, speed is faster than logic built from the same fundamental transistors and unhampered by the “Weak inversion” stage that has higher gains like bipolar transistors. As opposed to bipolar transistors, control current can go either in or out of the iPort control terminal 21b as well as operate with no iPort current, which is useful for creating a self-bias operating point.
Lower noise is facilitated by the self-biased operating point. Here the potential at drain terminal 29a or 29b is the same as potential at the gate control terminal 27a or 27b, greatly reducing the pinch-off effect found in conventional analog circuit designs.
The iFET 200, because of the common gate connection over the source channel 23a/23b and the drain channel 25a/25b, places a higher than expected voltage on the gate control terminal 27a/27b (or GS) of the source terminal 24a/24b or source channel 23a/23b. This higher than expected voltage is responsible for a much thicker and deeper (lower resistance highly ionized) conduction layer, allowing the majority of carriers to avoid the traps in the surface of the crystal lattice, hence—much lower noise similar to the manner in which a junction field effect transistor (or j-FET) conduction channel is located below the surface.
Trans-resistance (rm) is the “dual” of Trans-conductance (gm). When you look up Trans-resistance, most of the references are to inductors and capacitors, suggesting that the iFET may be useful in synthesizing inductors.
The iFET works in the following ways: A low noise amplifier requires a low impedance channel. A low impedance channel is low in voltage gain while high in current gain. To establish voltage gain, a second stage, operating as a current to voltage converter, is required. A cascaded pair provides such a configuration. Biasing requirements for a cascaded pair preclude its use at low voltage unless a solution for the biasing problem is found. The iFET provides the solution to this problem through self-biasing of a complementary pair. The impedance of the channel can be designed to accommodate the impedance of the particular signal source driving it (see later section on ratio).
Regarding FETs in general, carriers are attracted to the surface by the gate field, a low gate voltage creates a thin surface-layer on the channel (where the conductivity takes place) while a higher gate voltage creates a thicker under-layer. The thin layer of carriers is impeded by the non-uniform surface defects resulting in electrical noise, while a thicker layer of carriers finds a smoother path below the surface, thus reducing total electrical noise. This indicates that higher gate voltage translates to lower noise.
Injection current Iinj introduced into the iPort control terminal 21b increases the diffused charge (number of carriers per volume) over and in the source channel 23b, thus making the source channel 23b even more conductive. The rate of conductivity change is exponential, similar to that found in “weak inversion.” This exponential rate of conductivity change is due to the low voltage gradient along the source channel 23b (source terminal 24b to iPort control terminal 21b voltage gradient).
The iFET exponential relationship between source channel 23b charge and gate voltage 27b provides access to log functionality, where the addition of two log functions is equivalent to multiplication. A reverse anti-log, or reverse-exponential, operation recovers the analog output through the opposing complementary iFET channel. Such exponential relationship may be used for various low noise amplifier applications. The exponential relationship is also responsible for the wider dynamic range of these iFET circuits.
Again, referring to the source region in
The drain channel 25a of the iFET 200 of
Diffusion regions around the source region 24a of the iFET 200, operating at a low voltage, has lower voltage gain but it also has low noise. Diffusion region around the drain terminal 29a, operating at a higher voltage, provides the desired voltage gain with a minimal noise contribution, due to the drain voltage being the same as the gate voltage Vg. This voltage equality is contributed by a unique biasing construct, to be explained hereinafter.
Regarding the iPort control terminal, in the case of both the N-channel and P-channel devices, a positive current into the iPort control terminal displaces an equivalent current coming in through the drain channel, causing the drain (output) connection to move in a positive voltage direction—thus the non-Inverting nature of the iPort input.
The iPorts also operate as a current inverter as opposed to a conventional current mirror.
Interestingly, unlike other semiconductor devices, a negative current can be extracted from the iPort, causing a drain (output) shift in the negative direction. Zero input current is also valid.
An iFET 200 (as shown in
A P-channel device can be constructed and behaves in a similar fashion to its N-channel counterpart.
It should be emphasized that while the gate input is inverted with respect to the drain, the iPort is NOT inverted.
While a single iFET has interesting characteristics on its own, a complementary pair of iFETs (or CiFET) prove to be much more beneficial. Using the opposite semiconductor type iFET as a load device conveniently provides the opposing iFET its bias and in addition has the advantage of balancing out (linearizing) the inherent non-linarites of MOSFET operation. For instance, the high-gain exponential characteristics of the source channel'"'"'s super-saturated operation are linearized over an extremely wide dynamic range.
The resulting complementary device (the seminal CiFET cell) is arguably the highest possible power gain-bandwidth MOSFET amplifier stage possible. For instance, looking into either iPort, the super-saturated source channel input impedance is a relatively low number constant resistance. This converts any input current into a small input voltage, which calculates out to be a very high voltage gain transfer function implemented by the high number rm trans-resistance. In addition, the sub-surface operation of the super-saturated source channel may operate with the lowest noise possible for any MOS device. The drain channel also maximally operates below its surface defects for low noise. In the end it is all about signal-to-noise ratio.
In many analog circuits, biasing is a problem. Using iFETs in complementary pairs (31g & 32g) as shown in
In the “Behavioral Model” as shown in
The output (Vout 39f) is a low-impedance source follower common-gate FET configuration that can deliver its voltage with the necessary current to drive the following circuit.
The iPort input is a constant low resistance termination (related to rm but much lower) with a constant offset voltage, CTAT Ref, PTAT Ref, of about 1 mV to 100 mV from their respective power supply rail. This offset voltage is a “bandgap” reference, established by the ratio of the “drain channel” to “source channel” strength.
A standard CiFET compound device cell can be physically constructed and instantiated like a logic cell for designing analog. Normally this is the only active circuit component needed. Like a transistor, but the CiFET cell does everything needed for an active component.
How then is the proper bias voltage produced? The simplest way of generating the bias voltage is to use iFETs in complementary pairs, NiFET 31g and PiFET 32g, creating an inverting device as shown in
Since the complementary pair of iFETs 31g and 32g is self-biased, any parametric factors are auto-compensated, for changes in operating environment. Because of inherent matching between adjacent parts on an IC, the bias generator can be used to bias other iFETs nearby. The real-time self-biasing circuit corrects for parametric changes (in various forms).
Each of the transistors in an inverter of the present invention acts as a “dynamic” load for its complement, allowing the gate voltage to be significantly higher than the traditional bias point of an analog circuit gate. With the complementary iFET compound device'"'"'s higher than normal gate voltage, the source conduction channel is deep, yielding lower noise.
The dominant noise source in a traditional analog circuit is related to “pinch-off.” Biasing the drain (or output) at the same voltage as the gate (zero differential) causes the drain conduction channel to avoid the channel pinch-off (shallow channel) phenomena usually encountered in analog circuits. Another way of stating this is: a transistor gets noisier as the drain approaches its design maximum voltage, the self-biased inverter operates its transistors at around half the design maximum voltage and the gate is at the same voltage as the drain (zero differential), therefore the self-biased inverter is MUCH quieter.
The operation of the CiFET amplifier differs from the operation of a conventional analog amplifier, with its current mirror loads, in that:
The “Source” channel has an extremely small (−100 mv) voltage from source terminal to iPort control terminal while the “Gate terminal” is at ˜½ Vsupply. This puts the iFET Source channel into “Super-Saturation,” a condition similar to weak inversion but with high Gate overdrive. Gate overdrives resulting in an unusually thick conduction layer and along with a low Source to iPort voltage resulting in that conduction layer remaining thick all the way along the channel. Notice the differences in the thickness between the conduction channel 10s in
The “Drain” channel 25b operates with its'"'"' drain terminal 29b at ˜½ Vmax, greatly reducing the pinch-off (and DIBBL) effect. This reduced pinch-off condition is further enhanced by the fact that the “Gate terminal” is operated at ˜½ Vsupply (same as ˜½ Vmax), meaning no potential difference between the Drain 29b and the Gate 27b.
Another important aspect of the CiFET compound device is its current input that frees it from the speed robing effects of parasitic capacitance.
This subtle but significant difference is one of the enabling features that makes weak inversion work and gives the complementary iFET amplifier its superior low noise, wider dynamic range, and speed advantages.
MOSFETs do not make particularly good amplifiers compared to equivalent bipolar circuits. They have limited gain, they are noisy, and their high impedance makes them slow.
Bipolar Diff-Amps developed to the point where the input offset is pretty good, but the move to CMOS never really delivered as good a result.
It has long been known that superior performance can be had from CMOS operated in weak inversion but complications arising from high impedance, due to impractically low currents, preclude taking advantage of the superior gain (equivalent to that of bipolar transistors), dynamic range (exceeding that of bipolar transistors), and logarithmic performance (allowing numerous decades of amplification) found in weak inversion. Because of weak inversion the CiFET brings the noise benefits of majority carriers in a deep channel found in junction-FETs to the MOSFET.
While a MOSFET in weak inversion, working into a current source load, delivers a logarithmic transfer function, the same MOSFET working into an anti-log load cancels the nonlinearity, yielding a perfectly linear transfer function. The CiFET amplifier is such a circuit, i.e.: log input, antilog load, perfectly linear, wide dynamic range, low noise. The low noise is a consequence of the biasing, where the source channel gate potential is unusually high and the potential across the source channel itself is maintained at near zero volts. The drain channel is a level shifter, maintaining a very low voltage on the source channel while delivering high amplitude signal swings at the output.
The CiFET amplifier, implemented in a closed-loop, sample-data block delivers near perfect performance in terms of input offset because of its “flying capacitor” input. The CiFET amplifier, implemented in an open-loop, delivers unexpected levels of sensitivity (gain >1 million), even in the presence of high levels of background, this because of the extreme dynamic range.
Traditionally engineers have avoided using digital logic in an analog configuration because it was believed to be unacceptably nonlinear and was difficult to bias. Digital logic also sacrifices drive symmetry for compactness. Restoring the symmetry through proper device ratioing (˜3:1 p:n width) improves linearity, increases noise immunity, and maximizes dynamic range. Self-biasing solves the bias problem.
In order to maintain a high intrinsic gain, the MOSFET requires a high output impedance. This is obtained through long channel lengths necessary for high ro=Rout. Since gm is proportional to the W/L ratio of the MOSFET, in order to keep gm high when the channel is long, the channel must also be proportionally wider. Gain here is ˜gmRL/Rout. As the IC process shrinks, gm increases, but Rout decreases faster, ruling out short channel lengths for analog. This is why as IC processes shrink analog transistors do not scale accordingly in the newest double-digit CMOS technologies. Also, it is to be noted that the analog channel current travels close to the surface under the gate where the surface defect carrier traps create the characteristic MOSFET 1/f noise.
FinFETs have short nanoscale channel lengths that increase gm while lowering the drain output resistance of the bare field effect transistor. Higher gm provides better control over channel conductance, but the close proximity of the drain to the source makes them talk to each other making the output resistance low. This yields a low intrinsic gain of the MOSFET at nanoscale dimensions. Conversely the CiFET is a low output resistance device and improves with deep scaling.
According to the preferred embodiment of the present invention, noise figures can be particularly optimized on front end amplifiers through proper ratioing. The iFET'"'"'s electrical characteristics can be enhanced by modifying the combined and relative strength of the source and drain channels, without modifying the available IC process (without analog extensions). There are several approaches to realizing this optimization (adjusting length, width, and threshold among others).
Nearly any source and drain channel size will make a functional iFET, but varying the individual iFET channel size, both relative and cumulative, increases the iFET performance depending on the objective.
- Lower iPort impedance is achieved with a lower current density (wider) source channel as compared to the drain channel.
- Higher voltage gain is obtained through a higher resistance (longer) drain channel as compared to the source channel, which makes a higher output impedance looking into the drain terminal (iFET Voltage gain=Drain channel resistance/Source channel resistance).
- The power verses speed tradeoff is controlled by the cumulative sum of all of the channel strengths used to set the idle current through the complementary iFET amplifier. This establishes the output slew rate (or output drive capability).
To be clear, the strength of the iFET channels are a function of the individual channel width and lengths, as well as their thresholds. Each of the iFET channels can have individually selected sizes and/or threshold relationships to the other channel.
While iFET amplifiers can be constructed with minimum sized devices which do provide ample current at the output for very fast response and high accuracy, care must be exercised so that the complementary iFET amplifier does not pass too much current, subjecting it to mechanical failure. The physical layout requires enough contacts and metal for the required DC and transient currents.
Referring to a currentheld-effect transistor (iFET) in
Super-saturation current field transistor (or xiFET) includes a source terminal 44a, a drain terminal 49a, iPort (or diffusion) terminal 41a on a body 46a. A drain channel 45a is defined between iPort terminal 41a and the drain terminal 49a, and source channel 43a between the iPort terminal 41a and the source terminal 44a. A first gate terminal 47a1 is capacitively coupled over the drain channel 45a; while the second gate terminal 47a2 is capacitively coupled over the source channel 43a. This iFET improvement in xiFET 400 provides, instead of the common gate 27a/27b or a method of the iFET illustrated in
By adjusting voltage Vsg at the gate s47as with an independent signal source v47a2, the iPort input impedance can be electrically controlled. This is particularly useful for matching the input impedance of an antenna or transmission line to minimize reflections and maximize input power transfer into the iPort 41a. This additional source channel gate input also can be used to control the iPort trans-impedance gain, establishing a voltage controlled amplifier gain application. Also the source channel gate input 47a2 can be used to turn the xiFET 400 off and on rapidly to cut off its drain current when not needed in order to save power. The xiFET turn-on is nearly instantaneous in that the bias point at the iPort 41a is low impedance and does not need to settle as compared with conventional analog current mirrors. When turned off, the xiFET output is high impedance, thus when multiple xiFET voltage outputs are tied together and individual xiFETs are enabled, an array of xiFETs can be used as an analog multiplexer.
This property is especially useful in focal plane array (FPA) readouts. Here the FPA core is not changed at all, but only the readout line drive voltages are controlled differently to operate the existing two transistor pixel readout transistors as an xiFET. The low noise, high speed, high dynamic range, low power properties work in concert to create a high-quality FPA.
When either of the second gate terminals 57−a, 57+a are taken to their respective power supply rail, the CxiFET 501, 502 is turned OFF, thus saving power when the amplifier is not in use. Because of the large and uniform distribution of source channel ionized charge carriers, and low channel iPort voltage change between OFF to saturated, and back OFF is extremely fast, approaching logic speed for analog signals. The source channel quickly cuts OFF or immediately reaches its stable bias point. The low resistance and minimal voltage change drive rapid exponential settling to a stable bias point.
In addition, when either or both second gates 57−a, 57+a are taken to an intermediate voltage, the current through the CxiFET device 500 from Power+ to Power− and trans-impedance rm gain is controlled, making gain and power consumption verses speed electrically controllable. When these source channel gates are switched to the common gate voltage, the CxiFET becomes a CiFET.
When the CxiFET is used for charge-coupled logic, inputs on these second gates 57−a, 57+a can be used to turn the logic ON or OFF as well as strobe the logic state with a clock as appropriate.
It can also be a cross-coupled latch control where a pulse of charge flips the latch and due to the low voltage operating properties the latched state can be held with almost zero current consumption as shown in
In the “iFET,” the source channel is tied to a common, single gate. In the “xiFET,” the source channel gate is taken to an independent normally higher voltage than the drain channel gate voltage, to increase the source channel'"'"'s super-saturation level. Thus the input resistance at the iPort is controlled by this separate source channel'"'"'s gate voltage input. This configuration is tied to the proportional-to-absolute temperature (or PTAT)/complementary-to-absolute temperature (or CTAT) coefficient of the termination voltage of the iPort, as well as the magnitude of the trans-impedance gain (rm). It can be modeled as two separate FET transistors, with an iPort current input in the connection between their series hookup. Using this as a well-behaved linear analog bi-directional current/charge input/output is unique, which leads to a methodology of creating a trans-impedance MOSFET with separate electrically controllable rm gain and input resistance and input termination voltage. This is a method of adjusting the PTAT/CTAT iPort reference voltages and temperature properties electrically.
In general, the iFET/CiFET and the xiFET/CxiFETs are a new type of analog circuit element, or type, that operates in a charge-injection mode, yielding a trans-resistance amplifier (or more generally a trans-impedance amplifier) which creates a unique, predictable, parametrically stable, and very useful analog gain block. The advantage of this device is its stability, linearity, high-gain, high-speed, low-noise, unprecedented low voltage operation not limited by threshold voltage, high output drive, low power, small, and built out of digital-only IC parts.
Various degrees of complementary cancellation result from the opposite diffusion types of symmetry.
This yields an extremely linear transfer function obtained by the same circuit in the opposite diffusion type creating the complementary output signal drive. Thus, non-linearity and other errors cancel out at the output. We do not know of any analog circuit that considers this except a CMOS inverter with balanced transistors when it is roughly optimized for analog applications.
In the end, it comes down to signal-to-noise ratio. Low power supply voltage requirements in ultra-deep-sub-μm IC processes limit the maximum signal swing to a much smaller number than most analog designers are used to. So with a smaller signal, the noise must be equally small in order to maintain the desired signal to noise ratio. It is imperative that noise issues be reduced. This iFET amplifier technology not only reduces noise by an amount as would be necessary, but performs far beyond expectations, delivering ultra-quiet front ends.
1/f noise in the source channel is reduced because the self-bias scheme provides a high field strength on the source channel'"'"'s gate, forcing carriers in the channel to operate below the surface where there is a smoother path (fewer obstructions) than along the surface where crystal lattice defects interfere.
1/f noise in the drain channel is also low. Unlike conventional analog designs, the gate is self-biased at the half-way point between the power supply rails as is the drain, while the iPort is within ˜100 millivolts of the power rail. With the high electric field along the drain channel, and the gate voltage equal to the drain terminal voltage, the carriers are constrained to flow mostly below the channel surface. This keeps the drain channel out of pinched off conditions, where unwanted 1/f noise would be generated.
Resistor noise is reduced because the self-bias configuration puts the complementary pair at its lowest channel resistance operating point. Resistance is caused by collisions, between carriers and the surrounding atoms in the conductor. The lower the resistance is, the fewer the collisions are.
Wide band noise (white-noise) would always be an issue in high gain for high frequency circuits. While conventional designs adjust the gate voltage to establish suitable operating point(s), the designs of the present invention establish the gate voltage at the optimum point (the “sweet-spot”) and then adjust the load to establish the desired operating point. This approach establishes a higher quiescent current where (for reasons explained above) higher current density circuits have lower wide band noise.
High common mode power supply rejection is inherent in the complementary iFET circuit of the present invention. Signals are with respect to the mid-point instead of being with respect to one of the power supply rails, (similar to an op-amp with its “virtual” ground). Power supply noise is from one rail to the other, equal and opposite in phase with respect to each other; thus canceling around the mid-point.
Ground-Loop noise is diminished because the circuit ground is “virtual” (just like in many op-amp circuits), rather than ground being one or the other power supply connections. . . . In the closed-loop case, “Flying capacitors” (or “input voltage sampling capacitors”) are employed. With “flying capacitors” there is no direct electrical connection between stages, so there is no common ground; virtual or otherwise. The use of “differential decoupling” (flying capacitors) offers transformer like isolation between stages, with the compactness of integrated circuit elements.
Coupled noise from “parasitic induced crosstalk” increases by the square of the signal amplitude. Unintended capacitive coupling with a 1 volt signal causes a lot more trouble than with a 100 mV signal, by a factor of 100:1 (square law effect). The small voltage signals employed in the analog sections, reduce this capacitive coupled interference substantially. Nearby Digital signals will, by definition, be high amplitude (rail-to-rail). Good layout practices are still the best defense against this digital source of noise.
There are a number of additional advantages. For example, bi-directional control on the iPort means that current can flow in-to as well as out of this connection; both directions having a significant control effect on overall channel current. The iPort has about five (5) orders of magnitude more dynamic control range than the gate.
The iFET of the present invention yields an analog structure that is significantly faster than logic using the same MOS devices. This speed improvement is due to the fact that the complementary structure expresses its maximum gain (and highest quiescent current) at its natural self-bias point, midway between the power supplies.
Since the iPort voltage does not significantly change, it is immune to the R/C time constant effects of the surrounding parasitics, thus the iPort (current) input responds faster than the gate (voltage) input.
Since in most applications of the CiFET compound device of the present invention, the output voltage (drain connection point) does not vary greatly, and thus making the output immune to the R/C time constant effects of the surrounding parasitics. A logic signal is slower than analog here because logic signals have to swing from rail to rail.
Drain-induced barrier lowering or (DIBL) threshold reduction is avoided in the CiFET compound device operating in the analog mode. When gain and threshold voltage is important, the drains are operating around half of the power supply voltage, thus eliminating the higher drain voltages where DIBL effects are prevalent.
The circuit 80a shows a single core pixel element PX80, along with the current mirror Q84 and Q85 that pulls a current 801load down from each of the parallel columns to bias source follower Q82 for applying the respective Pixel voltage to its column ADC U80. The row of pixels is selected by logically turning on the Row-Select MOSFET Switch Q83 by row select signal 80Rsel inside each of the selected row pixels PX80. The respective column bias currents are routed form Vdd in each pixel through the pixel Source-Follower Q82; which in effect outputs the Photo-Diode node PD80 voltage 80aVfd, minus the operating threshold of the source follower Q82. Neither of these two Pixel transistors provide gain, they just pass the Vfd pixel voltage 80aVfd to the long full array readout column 80RC, making the pull-up relatively stiff, but leaving the pull down weak, due to the high impedance current source output, for (hiving the high capacitance column bus in one direction, but not the other.
As it can be seen in comparison of
The equivalent circuit 80d in
The gain controllable bias generator 80e includes a complementary pair of NiFET N86 and PiFET P86, each of which includes a source terminal N86a/P86a, iPort terminal N86b/P86b, drain terminal N86c/P86c, and gate terminal N86d/P86d. The source terminal N86a of NiFET N86 receives negative power supply Vss and the source terminal P86a of PiFET P86 receives positive power supply Vdd. The iPort terminal P86b of PiFET P86 receives gain control signal gc80e . The gate terminals N86d and P86d, and the drain terminals N86c and P86c are coupled together as output out80e which is bias voltage generated by the present circuit 80e.
The comparator COMP includes two CiFET 300a and 300b, each of which are the same as CiFET 300 shown in
During the “SETUP” phase of the control signal, the first and second switches SS90a, SS90b, and SS90c and ES90a and ES90b causes to couple the positive voltage output 79m of the CTIA 710m with the first terminal of the first capacitor COS90a, causes the first CiFET 300a to be self-biased by connecting its output to its input, and further causes the second CiFET 300b to be self-biased by connecting its output to its input, while the second capacitor COS90b stores any slight offset voltage difference between these two self-bias voltages.
At the beginning of the “ENABLE” phase of the control signal, the first and second switches SS90a, SS90b, and SS90c and ES90a causes the difference between the positive voltage 79m and the negative voltage 78m to be instantly coupled to the first and second terminals of the first capacitor COS90a, and through to the input of the first latch CiFET 300a input. After a brief logic buffer propagation delay, the output switch ES90b of the second CiFET 300b is closed through to the input of the first CiFET 300a forming a rapid AC positive feedback latching loop. This brief logic buffer delay allows the CiFETs 300a and 300b to start in their proper polarity direction as imposed by the difference of the TIA outputs 79m and 78m. Ideally, once the output of CiFET 300b begins to move, the positive feedback loop is closed driving the comparator latch all the way to its logical state rapidly to be passed onto the system which this comparator is embedded in.
For even greater comparator decision speed, the latching current comparator 900 may optionally have a feedforward capacitors CFF90p and CFF90n, which capacitively couple the input of the first CiFET 300a to iPorts of the second CiFET 300b.
iFET: A 4 terminal (plus body) device similar to a Field Effect Transistor but with an additional control connection that causes the device to respond to current input stimulus.
source channel: A semiconductor region between iPort diffusion and the Source diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.
drain channel: A semiconductor region between Drain diffusion and the iPort diffusion. Conduction in this region is enabled by an appropriate voltage on the Gate.
CiFET: A single stage, complementary iFET compound device shown in
super-saturation: an exponential conduction condition similar to weak inversion, but with high Gate overdrive and forced low voltage along the conduction channel.
feed-forward: A technique to present a signal on an output, early on, in anticipation of the ultimate value.
self-biased: Unlike fixed-bias circuits, self-biased circuits adjust to local conditions to establish an optimum operating point.
dual: (of a theorem, expression, etc.) related to another by the interchange of pairs of variables, such as current and voltage as in “Trans-Conductance” to “Trans-Resistance.”
trans-resistance: infrequently referred to as mutual resistance, is the dual of Trans-conductance. The term is a contraction of transfer resistance. It refers to the ratio between a change of the voltage at two output points and a related change of current through two input points, and is notated as rm:
The SI unit for Trans-resistance is simply the ohm, as in resistance.
For small signal alternating current, the definition is simpler:
trans-impedance: similar to trans-resistance, but further includes complex variables for high frequency applications.
trans-conductance is a property of certain electronic components. Conductance is the reciprocal of resistance; Trans-conductance is the ratio of the current variation at the output to the voltage variation at the input. It is written as gm. For direct current, Trans-conductance is defined as follows:
For small signal alternating current, the definition is simpler:
Trans-conductance is a contraction of transfer conductance. The old unit of conductance, the mho (ohm spelled backwards), was replaced by the SI unit, the Siemens, with the symbol S (1 siemens=1 ampere per volt).
translinear circuit: translinear circuit is a circuit that carries out its function using the translinear principle. These are current-mode circuits that can be made using transistors that obey an exponential_current-voltage characteristic—this includes BJTs_and CMOS transistors in weak inversion.
subthreshold conduction or subthreshold leakage or subthreshold drain current is the current_between the source and drain of a MOSFET when the transistor is in subthreshold region, or weak-inversion region, that is, for gate-to-source voltages below the threshold voltage. The terminology for various degrees of inversion is described in Tsividis. (Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor_(Second Edition ed.). New York: McGraw-Hill. p. 99, ISBN 0-07-065523-5.)
Subthreshold slope: In the subthreshold region the drain current behavior—though being controlled by the gate_terminal—is similar to the exponentially increasing current of a forward biased diode. Therefore a plot of logarithmic drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately log linear behavior in this MOS FET operating regime. Its slope is the subthreshold slope.
Diffusion current: Diffusion current is a current_in a semiconductor_caused by the diffusion_of charge carriers (holes and/or electrons), Diffusion current can be in the same or opposite direction of a drift current, that is formed due to the electric field_in the semiconductor. At equilibrium in a p-n junction, the forward diffusion current in the depletion region is balanced with a reverse drift current, so that the net current is zero. The diffusion current and drift current together are described by the drift-diffusion equation.
Drain-induced barrier lowering: Drain-induced barrier lowering or DIBL is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage_of the transistor_at higher drain voltages.
As channel length decreases, the barrier φB to be surmounted by an electron from the source on its way to the drain reduces.
As channel length is reduced, the effects of DIBL in the subthreshold region (weak inversion) show up initially as a simple translation of the subthreshold current vs. gate bias curve with change in drain-voltage, which can be modeled as a simple change in threshold voltage with drain bias. However, at shorter lengths the slope of the current vs. gate bias curve is reduced, that is, it requires a larger change in gate bias to effect the same change in drain current. At extremely short lengths, the gate entirely fails to turn the device off. These effects cannot be modeled as a threshold adjustment.
DIBL also affects the current vs. drain bias curve in the active mode, causing the current to increase with drain bias, lowering the MOSFET output resistance. This increase is additional to the normal channel length modulation effect on output resistance, and cannot always be modeled as a threshold adjustment.
PSSR stands for power supply rejection ratio, defined as:
where A is the gain of the circuit. Some manufacturers base PSSR on the offset voltage to the amplifier input and others base the PSSR on the voltage output as shown in the example equation.