STROBE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

• US 20190253041A1
• Filed: 04/23/2019
• Published: 08/15/2019
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Young-Hoon
• Granted Patent: US 10,727,824 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/356191 with synchronous operation
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A strobe generation circuit includes: a main hybrid multiplexing circuit outputting a main pull-up signal and a main pull-down signal to first and second nodes, respectively, the main pull-up and pull-down signals being selectively controlled based on first pull-up and pull-down control signals generated by removing an input loading of main data; a sub hybrid multiplexing circuit outputting a sub pull-up signal and a sub pull-down signal to the first and second nodes, respectively, the sub pull-up and pull-down signals being selectively controlled based on second pull-up and pull-down control signals generated by removing an input loading of sub data; a latch circuit latching a signal of the first node and a signal of the second node to output a first latch signal and a second latch signal; and an output driver outputting a strobe signal according to the first and second latch signals.

Claims

1. A strobe generation circuit, comprising:

a main hybrid multiplexing circuit suitable for outputting a main pull-up signal and a main pull-down signal to a first node and a second node, respectively, the main pull-up signal and the main pull-down signal being selectively controlled based on a first pull-up control signal and a first pull-down control signal, which are generated by removing an input loading of a plurality of main data inputted to the main hybrid multiplexing circuit;

a sub hybrid multiplexing circuit suitable for outputting a sub pull-up signal and a sub pull-down signal to the first node and the second node, respectively, the sub pull-up signal and the sub pull-down signal being selectively controlled based on a second pull-up control signal and a second pull-down control signal, which are generated by removing an input loading of a plurality of sub data inputted to the sub hybrid multiplexing circuit;

a latch circuit suitable for latching a signal of the first node and a signal of the second node to output a first latch signal and a second latch signal; and

an output driver suitable for outputting a strobe signal according to the first latch signal and the second latch signal.

2. The strobe generation circuit of claim 1, further comprising:

a main trigger circuit suitable for latching input data based on a plurality of main clocks to output the plurality of main data; and

a sub trigger circuit suitable for latching preliminary data based on a plurality of sub clocks to output the plurality of sub data.

3. The strobe generation circuit of claim 2,

wherein the plurality of main clocks toggle with a set phase difference during a data input/output period, and

wherein the plurality of sub clocks include a first group which toggles with the set phase during a preamble period before the data input/output period, and a second group which toggles with the set phase during a postamble period after the data input/output period.

4. The strobe generation circuit of claim 2, wherein the main trigger circuit differentially amplifies the input data during an activation section of the main clocks to output a plurality of main data and a plurality of complementary main data.

5. The strobe generation circuit of claim 4, wherein the main trigger circuit includes:

a plurality of trigger units corresponding to the main clocks,

each of the plurality of trigger units being suitable for differentially amplifying the input data to output the main data and the complementary main data when a corresponding main clock is a first logic level, and pre-charging the main data and the complementary main data to a certain level when the corresponding main dock is a second logic level.

6. The strobe generation circuit of claim 4, wherein the main hybrid multiplexing circuit includes:

a first static logic unit suitable for generating the first pull-down control signal by removing an input loading of the main data, and generating the first pull-up control signal by removing an input loading of the complementary main data; and

a first dynamic logic unit suitable for selectively driving the main pull-up signal and the main pull-down signal based on the first pull-down control signal and the first pull-up control signal, and outputting the main pull-up signal and the main pull-down signal to the first node and the second node, respectively.

7. The strobe generation circuit of claim 2, wherein the sub trigger circuit differentially amplifies the preliminary data during an activation section of the sub clocks to output a plurality of sub data and a plurality of complementary sub data.

8. The strobe generation circuit of claim 7, wherein the sub trigger circuit includes:

a plurality of trigger units corresponding to the sub clocks,

each of the plurality of trigger units suitable for differentially amplifying the preliminary data to output the sub data and the complementary sub data when a corresponding sub clock is a first logic level, and pre-charging the sub data and the complementary sub data to a certain level when the corresponding sub clock is a second logic level.

9. The strobe generation circuit of claim 7, wherein the sub hybrid multiplexing circuit includes:

a second static logic unit suitable for generating the second pull-down control signal by removing an input loading of the sub data, and generating the second pull-up control signal by removing an input loading of the complementary sub data; and

a second dynamic logic unit suitable for selectively driving the sub pull-up signal and the sub pull-down signal based on the second pull-down control signal and the second pull-up control signal, and outputting the sub pull-up signal and the sub pull-down signal to the first node and the second node, respectively.

10. The strobe generation circuit of claim 1, further comprising:

a section control circuit suitable for controlling an entry to a preamble period of the strobe signal according to a first section control signal, and controlling an exit from a postamble period of the strobe signal according to a second section control signal.

11. The strobe generation circuit of claim 10, wherein the section control circuit includes:

a first section controller suitable for driving the second node to a first logic level according to the first section control signal, and driving the second node to a second logic level according to the second section control signal; and

a second section controller suitable for driving the first node to the second logic level according to the second section control signal.

12. A semiconductor device, comprising:

a first strobe generation circuit suitable for latching input data and preliminary data based on a plurality of main clocks and a plurality of sub clocks to output a plurality of first main data and a plurality of first sub data, generating first and second control signals by removing an input loading of the first main data and the first sub data, and generating a first strobe signal according to the first and second control signals; and

a second strobe generation circuit suitable for latching inverted input data and inverted preliminary data based on the main clocks and the sub clocks to output a plurality of second main data and a plurality of second sub data, generating third and fourth control signals by removing an input loading of the second main data and the second sub data, and generating a second strobe signal according to the third and fourth control signals,

wherein the first strobe generation circuit has substantially the same logic configuration as the second strobe generation circuit.

13. The semiconductor device of claim 12,

wherein the plurality of main clocks toggle with a set phase difference during a data input/output period,

wherein the plurality of sub clocks include a first group which toggles with the set phase during a preamble period before the data input/output period, and a second group which toggles with the set phase during a postamble period after the data input/output period.

14. The semiconductor device of claim 12, wherein the first strobe generation circuit includes:

a first main trigger circuit suitable for latching the input data based on the main clocks to output the plurality of first main data;

a first sub trigger circuit suitable for latching the preliminary data based on the sub clocks to output the plurality of first sub data;

a first main hybrid multiplexing circuit suitable for outputting a first driving signal which is selectively controlled based on the first control signal generated by removing the input loading of the first main data;

a first sub hybrid multiplexing circuit suitable for outputting a second driving signal which is selectively controlled based on the second control signal generated by removing the input loading of the first sub data; and

a first output driver suitable for outputting the first strobe signal according to the first driving signal and the second driving signal.

15. The semiconductor device of claim 12, wherein the second strobe generation circuit includes:

a second main trigger circuit suitable for latching the inverted input data based on the main clocks to output the plurality of second main data;

a second sub trigger circuit suitable for latching the inverted preliminary data based on the sub clocks to output the plurality of second sub data;

a second main hybrid multiplexing circuit suitable for outputting a third driving signal which is selectively controlled based on the third control signal generated by removing the input loading of the second main data;

a second sub hybrid multiplexing circuit suitable for outputting a fourth driving signal which is selectively controlled based on the fourth control signal generated by removing the input loading of the second sub data; and

a second output driver suitable for outputting the second strobe signal according to the third driving signal and the fourth driving signal.

16. A strobe generation circuit comprising:

a main hybrid multiplexing circuit suitable for receiving a plurality of main data, generating a first pull-up control signal and a first pull-down control signal based on levels of the plurality of main data, and outputting the main pull-up signal and the main pull-down signal to a first node and a second node, respectively, by driving the first node according to the first pull-up control signal and driving the second node according to the first pull-down control signal;

a sub hybrid multiplexing circuit suitable for receiving a plurality of sub data, generating a second pull-up control signal and a second pull-down control signal based on levels of the plurality of sub data, and outputting the sub pull-up signal and the sub pull-down signal to the first node and the second node, respectively, by driving the first node according to the second pull-up control signal and driving the second node according to the second pull-down control signal;

a latch circuit suitable for latching a signal of the first node and a signal of the second node to output a first latch signal and a second latch signal;

a section control circuit suitable for driving the first node and the second node as set levels, based on an entry of a preamble period and an exit from a postamble period; and

an output driver suitable for outputting, to an output node, a strobe signal according to the first latch signal and the second latch signal.