MEMORY DEVICE DETERMINING OPERATION MODE BASED ON EXTERNAL VOLTAGE AND METHOD OF OPERATING THE SAME

• US 20190259429A1
• Filed: 08/14/2018
• Published: 08/22/2019
• Est. Priority Date: 02/20/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HEO, JIN-SEOK, MOON, JOUNG-WOOK, KIM, KI-HO, BAEK, JIN-HYEOK, HYUN, SEOK-HUN
• Granted Patent: US 10,643,675 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.

Claims

1. A memory device comprising:

a cell array comprising a plurality of memory cells;

a mode selector configured to detect a level of at least one voltage signal externally provided and select any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal;

a mode controller configured, in response to a mode selecting signal from the mode selector, to output setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and

a calibrating circuit configured to generate a control code for controlling circuit blocks in the memory device according to the setting information.

2. The memory device of claim 1, wherein the mode selector receives a first power voltage and a second power voltage as the at least one voltage signal from an external power management integrated circuit (PMIC), and is configured to generate the mode selecting signal by detecting a difference between a level of the first power voltage and a level of the second power voltage.

3. The memory device of claim 1, wherein the memory device communicates with the memory controller via the interface according to a low power double data rate 4 (LPDDR4) standard or a low power double data rate 4X (LPDDR4X) standard,

the at least one voltage signal includes a first power voltage and a second power voltage defined in the LPDDR4 standard and the LPDDR4X standard, and

the mode selector is configured to select one of a first operation mode from among the plurality of operation modes for performing the interface according to the LPDDR4 standard and a second operation mode from among the plurality of operation modes for performing the interface according to the LPDDR4X standard, based on a result of detecting a difference between a level of the first power voltage and a level of the second power voltage.

4. The memory device of claim 3, wherein the mode selector comprises a voltage divider configured to divide the second power voltage and a comparator, and

the comparator is configured to generate the mode selecting signal by comparing the level of the first power voltage with a voltage level generated as a result of dividing the second power voltage.

5. The memory device of claim 1, wherein the circuit blocks comprise an output driver for outputting read data to the memory controller, and

the calibrating circuit is configured to generate as the control code a first control code for adjusting a voltage level of the read data to a first level in response to the setting information when a first operation mode from among the plurality of operation modes is set, and for adjusting the voltage level of the read data to a second level in response to the setting information when a second operation mode from among the plurality of operation modes is set.

6. The memory device of claim 5, wherein the circuit blocks further comprise an on-die termination (ODT) circuit configured to provide a termination resistor during a data write operation, and

the calibrating circuit is configured to generate as the control code a second control code for enabling the ODT circuit in response to the setting information when the first operation mode is set and disabling the ODT circuit in response to the setting information when the second operation mode is set.

7. The memory device of claim 1, wherein responsive to a calibrating command provided by the memory controller, the mode selector is configured to generate the mode selecting signal before a calibrating operation is performed.

8. The memory device of claim 7, wherein the mode selector is configured to selectively generate the mode selecting signal when the calibrating command provided by the memory controller corresponds to an initial calibrating command

9. The memory device of claim 1, wherein the mode controller comprises a mode register set (MRS) configured to store mode register information having a plurality of pieces of field information provided by the memory controller,

the mode controller is configured to output as the setting information first setting information for the interface according to a low power double data rate 4 (LPDDR4) standard through a first decoding operation on the plurality of pieces of field information when a first operation mode according to the LPDDR4 standard is selected from among the plurality of operation modes, and

the mode controller is configured to output as the setting information second setting information for the interface according to a low power double data rate 4X (LPDDR4X) standard through a second decoding operation on the plurality of pieces of field information when a second operation mode according to the LPDDR4X standard is selected from among the plurality of operation modes.

10. A memory device comprising:

a memory cell array comprising a plurality of memory cells;

a mode selector configured to detect a level of at least one power voltage externally provided and select one of a low power double data rate 4 (LPDDR4) standard mode and a low power double data rate 4X (LPDDR4X) standard mode as a standard for interfacing with a memory controller according to a result of detecting the level of the at least one power voltage;

a mode controller configured to output setting information corresponding to a selected standard mode in response to a mode selecting signal from the mode selector; and

a calibrating circuit configured, in response to the setting information from the mode controller, to generate a first control code for adjusting a voltage level of output data of the memory device to a first level in the LPDDR4 standard mode and adjusting the voltage level of the output data of the memory device to a second level in the LPDDR4X standard mode, the second level being different from the first level.

11. The memory device of claim 10, wherein the mode selector receives a first power voltage that powers an input/output circuit of the memory device and a second power voltage that powers a peripheral circuit, and the mode selector is configured to select the LPDDR4 standard mode or the LPDDR4X standard mode according to a difference between a level of the first power voltage and a level of the second power voltage.

12. The memory device of claim 10, further comprising an output driver configured to generate the output data, wherein the output driver comprises a pull-up unit comprising one or more first transistors and a pull-down unit comprising one or more second transistors, wherein the calibrating circuit comprises:

a first comparator configured to compare a level of a first internal voltage with a level of a first reference voltage, and generate a first comparison result;

a first counter configured to generate a first control code for controlling the one or more second transistors of the pull-down unit based on the first comparison result; and

a reference voltage generator configured to generate the first reference voltage and adjust the first reference voltage differently in the LPDDR4 standard mode and the LPDDR4X standard mode in response to the setting information.

13. The memory device of claim 12, wherein the calibrating circuit further comprises:

a second comparator configured to compare a level of a second internal voltage with a level of a second reference voltage, and generate a second comparison result; and

a second counter configured to generate a second control code for controlling the one or more first transistors of the pull-up unit based on the second comparison result,

wherein the reference voltage generator is further configured to generate the second reference voltage and adjust the second reference voltage differently in the LPDDR4 standard mode and the LPDDR4X standard mode in response to the setting information.

14. The memory device of claim 13, further comprising an on-die termination (ODT) circuit,

wherein the calibrating circuit is configured, in response to the setting information from the mode controller, to generate the first control code for controlling the ODT circuit to any one of an enabled state and a disable state in the LPDDR4 standard mode and controlling the ODT circuit to another one of the enabled state and the disable state in the LPDDR4X standard mode.

15. A method of operating a memory device comprising a mode selector and a calibrating circuit, the method comprising:

receiving at the mode selector a first command and one or more power voltages during an initial operation of a system;

detecting, by the mode selector, levels of the one or more power voltages in response to reception of the first command;

selecting, by the mode selector, an operation mode corresponding to any one selected from among a plurality of standards according to a result of detecting the levels of the one or more power voltages; and

performing, by the calibrating circuit, a calibrating operation to adjust a voltage level of output data of the memory device and enable/disable an on-die termination (ODT) circuit according to the selected operation mode.

16. The method of claim 15, wherein the first command corresponds to an initial calibrating command during the initial operation of the system, and

the selecting of the operation mode is performed before an initial calibrating operation corresponding to the initial calibrating command is started.

17. The method of claim 15, wherein the memory device communicates with an external memory controller selectively via an interface according to one of a low power double data rate 4 (LPDDR4) standard and a low power double data rate 4X (LPDDR4X) standard, and

wherein said performing the calibrating operation comprises setting the voltage level of the output data to a first level to perform an interface according to the LPDDR4 standard, and setting the voltage level of the output data to a second level to perform an interface according to the LPDDR4X standard.

18. The method of claim 17, wherein said performing the calibrating operation comprises setting the ODT circuit to any one of an enabled state and a disabled state at the interface according to the LPDDR4 standard, and setting the ODT circuit to another one of the enabled state and the disabled state at the interface according to the LPDDR4X standard.

19. The method of claim 17, wherein said detecting the levels of the one or more power voltages comprises comparing a voltage level difference between a first power voltage and a second power voltage defined in the LPDDR4 standard and the LPDDR4X standard with a threshold value.

20. The method of claim 17, wherein said selecting the operation mode comprises selecting a first operation mode corresponding to the LPDDR4 standard,

the method further comprising setting the operation mode of the memory device to a second operation mode corresponding to the LPDDR4X standard according to a result of said detecting the levels of the one or more power voltages received after the system is re-booted.