SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES

• US 20190259440A1
• Filed: 03/19/2018
• Published: 08/22/2019
• Est. Priority Date: 02/17/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Michael V.
• Granted Patent: US 10,460,791 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

Claims

1. A semiconductor device, comprising:

a plurality of memory banks;

an output buffer configured to couple to the plurality of memory banks;

a plurality of switches configured to couple a voltage source to the output buffer; and

a stagger delay circuit, comprising;

a resistor-capacitor (RC) circuit configured to output a current signal that corresponds to a data voltage signal received by the RC circuit; and

a logic circuit configured to;

determine a strength of the current signal; and

send a first gate signal to a first portion of the plurality of switches based on the strength, wherein the first gate signal is configured to cause each of the first portion of the plurality of switches to close.

2. The semiconductor device of claim 1, wherein the logic circuit is configured to send the first gate signal in response to a current value of the current signal being above a first threshold.

3. The semiconductor device of claim 1, wherein the current signal is configured to decrease in value while charging a capacitor of the RC circuit.

4. The semiconductor device of claim 1, wherein the logic circuit is configured to send a second gate signal to a second portion of the plurality of switches in response to a current value of the current signal being below a first threshold.

5. The semiconductor device of claim 4, wherein the logic circuit is configured to send a third gate signal to a third portion of the plurality of switches in response to the current value of the current signal being below a second threshold.

6. The semiconductor device of claim 5, wherein a first time interval between sending the first gate signal and sending the second gate signal is substantially equal to a second interval between sending the second gate signal and the third gate signal.

7. The semiconductor device of claim 1, wherein the logic circuit is configured to adjust a slew rate of a voltage signal provided to the output buffer.

8. The semiconductor device of claim 1, wherein the RC circuit comprises a plurality of fuses configured to adjust a resistance of the RC circuit.

9. A logic circuit, configured to:

receive a current signal from a resistor-capacitor (RC) circuit, wherein the current signal corresponds to data received by the RC circuit, wherein the output buffer is configured to be written or read via one or more memory banks;

determine a strength of the current signal;

transmit a first gate signal to a first set of switches configured to couple a voltage source to an output buffer configured to couple to the one or more memory banks in response to the strength being above a first threshold; and

transmit a second gate signal to a second set of switches configured to couple the voltage source to the output buffer in response to the strength being below the first threshold.

10. The logic circuit of claim 9, configured to transmit a third gate signal to a third set of switches configured to couple the voltage source to the output buffer in response to the strength being below a second threshold.

11. The logic circuit of claim 10, wherein a first time interval between the transmission of the first gate signal and the second gate signal is substantially equal to a second time interval between the transmission of the second gate signal and the third gate signal.

12. The logic circuit of claim 9, wherein the first threshold is determined based on a target slew rate of a voltage signal provided to the output buffer.

13. The logic circuit of claim 9, wherein each switch of the first set of switches and the second set of switches is coupled to each other in parallel.

14. The semiconductor device of claim 9, wherein the strength of the current signal corresponds to a current value of the current signal.

15. A method, comprising:

receiving, via a circuit, a current signal that corresponds to data to be written or read via one or more memory banks;

transmit, via the circuit, a first gate signal to a first set of switches configured to couple a voltage source to an output buffer, wherein the output buffer is configured to couple to the one or more memory banks in response to the strength of the current signal being above a first threshold;

transmit, via the circuit, a second gate signal to a second set of switches configured to couple the voltage source to the output buffer in response to the strength of the current signal being below the first threshold; and

transmit, via the circuit, a third gate signal to a third set of switches configured to couple the voltage source to the output buffer in response to the strength being below a second threshold.

16. The method of claim 15, wherein the first threshold and the second threshold are determined based on a target slew rate of a voltage signal applied to the output buffer via the voltage source, the first set of switches, the second set of switches, and the third set of switches.

17. The method of claim 16, wherein the target slew rate comprises a range of slew rates between a minimum slew rate and a maximum slew rate associated with the one or more memory banks.

18. The method of claim 15, wherein the first threshold and the second threshold are determined based on a first time interval between the transmission of the first gate signal and the second gate signal and a second time interval between the transmission of the second gate signal and the third gate signal.

19. The method of claim 15, wherein the strength of the current signal corresponds to a current value of the current signal.

20. The method of claim 15, wherein the current signal is configured to decrease in value while charging a capacitor of a resistor-capacitor (RC) circuit configured to receive the data.