METHODS FOR FORMING WRAP AROUND CONTACT

• US 20190259846A1
• Filed: 05/03/2019
• Published: 08/22/2019
• Est. Priority Date: 03/04/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Chan Syun David
• Granted Patent: US 10,790,370 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/263 with high-energy radiation H01L21/261 takes precedence
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor fin that extends from a substrate. The first semiconductor fin has source and drain regions, which are separated from one another by a channel region in the first semiconductor fin. A gate overlies an upper surface and sidewalls of the channel region. A contact is coupled to the source or drain region of the first semiconductor fin, where the source or drain region includes a layer of epitaxial material with a substantially diamond-shaped cross-section. The contact surrounds the source or drain region on top and bottom surfaces of the substantially diamond-shaped cross-section. A first capping material is arranged along outer sidewalls of the first semiconductor fin under the contact. The first capping material has an uppermost surface that is spaced below a lowermost surface of the contact by a non-zero distance.

Claims

1. A semiconductor device, comprising:

a first semiconductor fin extending from a substrate and through an isolation layer, the first semiconductor fin comprising a source region and a drain region;

a gate overlying the first semiconductor fin between the source region and the drain region;

a contact coupled to the source region or the drain region; and

a capping material disposed along a first sidewall of the first semiconductor fin, the capping material spaced from the contact.

2. The semiconductor device of claim 1, wherein the isolation layer contacts the substrate.

3. The semiconductor device of claim 1, wherein the capping material contacts the isolation layer.

4. The semiconductor device of claim 1, wherein a distance between opposite outermost sidewalls of the contact is greater than a distance between opposite outermost sidewalls of the first semiconductor fin.

5. The semiconductor device of claim 1, further comprising:

a second semiconductor fin extending from the substrate and through the isolation layer, wherein the first sidewall faces the second semiconductor fin.

6. The semiconductor device of claim 5, further comprising:

contact residue disposed over the substrate and between the first semiconductor fin and the second semiconductor fin.

7. The semiconductor device of claim 1, wherein the contact contacts the first sidewall.

8. The semiconductor device of claim 7, wherein the contact extends laterally away from the first sidewall and continuously over the first semiconductor fin to contact a second sidewall of the first semiconductor fin that is opposite the first sidewall.

9. The semiconductor device of claim 1, further comprising:

an epitaxial structure disposed on the first semiconductor fin, wherein a distance between opposite outermost sidewalls of the epitaxial structure is greater than a distance between opposite outermost sidewalls of the first semiconductor fin.

10. The semiconductor device of claim 9, wherein the contact extends from the first sidewall and wraps around a perimeter of the epitaxial structure to contact a second sidewall of the first semiconductor fin that is opposite the first sidewall.

11. The semiconductor device of claim 10, wherein the epitaxial structure has a substantially diamond-shaped cross-section.

12. A semiconductor device, comprising:

a first semiconductor fin extending from a substrate, wherein the first semiconductor fin comprises a source region and a drain region;

a second semiconductor fin extending from the substrate and laterally spaced from the first semiconductor fin;

a gate overlying the first semiconductor fin and the second semiconductor fin;

a contact coupled to the source region or the drain region; and

contact residue disposed over the substrate and between the first semiconductor fin and the second semiconductor fin, wherein the contact residue is spaced from the first semiconductor fin.

13. The semiconductor device of claim 12, wherein the contact residue is spaced from the second semiconductor fin.

14. The semiconductor device of claim 12, wherein the contact residue is spaced from the contact.

15. The semiconductor device of claim 12, wherein an uppermost surface of the contact residue is disposed below a bottommost surface of the contact.

16. The semiconductors device of claim 12, wherein both the contact and the contact residue comprise a same material.

17. The semiconductor device of claim 12, further comprising:

an epitaxial structure disposed on the first semiconductor fin, wherein a distance between opposite outermost sidewalls of the epitaxial structure is greater than a distance between opposite outermost sidewalls of the first semiconductor fin, and wherein the contact wraps around the epitaxial structure from a first side of the first semiconductor fin to a second side of the semiconductor fin opposite the first side.

18. A semiconductor device, comprising:

a first semiconductor fin extending from a substrate, wherein the first semiconductor fin comprises a source region and a drain region;

a second semiconductor fin laterally spaced from the first semiconductor fin and extending from the substrate;

a gate overlying the first semiconductor fin between the source region and the drain region;

a contact coupled to the source region or the drain region; and

a capping material disposed along a sidewall of the first semiconductor fin that faces the second semiconductor fin, wherein the capping material is spaced from the second semiconductor fin.

19. The semiconductor device of claim 18, wherein the capping material is spaced from the contact.

20. The semiconductor device of claim 19, further comprising:

an epitaxial structure disposed on the first semiconductor fin, wherein the epitaxial structure has a substantially diamond-shaped cross-section, and wherein the contact wraps around the epitaxial structure along outer sidewalls of the epitaxial structure from a first side of the first semiconductor fin to a second side of the semiconductor fin opposite the first side.