METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES

• US 20190267548A1
• Filed: 05/10/2019
• Published: 08/29/2019
• Est. Priority Date: 05/31/2016
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Miin-Jang, Pan, Samuel C., Hsieh, Chung-Yen
• Granted Patent: US 10,461,254 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: H10K 71/18 using non-liquid printing techniques, e.g. thermal transfer printing from a donor sheet
• CPC Class Codes: H10K 85/20 Carbon compounds, e.g. carbon nanotubes or fullerenes
• CPC Class Codes: H10K 85/221 Carbon nanotubes

Abstract

A method and structure for providing uniform, large-area graphene by way of a transfer-free, direct-growth process. In some embodiments, a SAM is used as a carbon source for direct graphene synthesis on a substrate. For example, a SAM is formed on an insulating surface, and a metal layer is formed over the SAM. The metal layer may serve as a catalytic metal, whereby the SAM is converted to graphene following an annealing process. The SAM is deposited using a VPD process (e.g., an ALD process and/or an MLD process). In some embodiments, a CNT having a controlled diameter may be formed on the surface of a nanorod by appropriately tuning the geometry of the nanorod. Additionally, in some embodiments, a curved graphene transistor may be formed over a curved oxide surface, thereby providing a band gap in a channel region of the graphene transistor.

Claims

1. A device, comprising:

a substrate having a first surface that includes a curved region;

a conformal graphene layer disposed over the substrate, wherein the conformal graphene layer includes a second surface that follows a first surface contour of the curved region to provide a curved graphene layer within the curved region; and

a source/drain electrode in contact with the conformal graphene layer outside the curved region.

2. The device of claim 1, wherein the substrate includes an insulating substrate.

3. The device of claim 2, wherein the insulating substrate includes one of quartz, glass, ceramic, sapphire, and silicon carbide (SiC).

4. The device of claim 1, further comprising:

an insulating layer disposed over the substrate, wherein the insulating layer includes a third surface that follows the first surface contour of the curved region to provide a curved insulating layer within the curved region;

wherein the conformal graphene layer is disposed over the insulating layer.

5. The device of claim 1, wherein the substrate further includes a substantially planar region disposed adjacent to and on either side of the curved region.

6. The device of claim 5, wherein the second surface of the conformal graphene layer follows a second surface contour of the substantially planar region to provide a substantially planar graphene layer adjacent to and on either side of the curved region.

7. The device of claim 1, wherein the curved region includes one of a concave region and a convex region.

8. The device of claim 1, wherein the conformal graphene layer includes one of monolayer graphene, bilayer graphene, and multi-layer graphene.

9. The device of claim 6, wherein the curved graphene layer includes semiconducting graphene, and wherein the substantially planar graphene layer includes metallic graphene.

10. The device of claim 1, wherein the curved graphene layer includes a channel region of the device.

11. The device of claim 1, further comprising:

a top-gate dielectric layer formed over the curved graphene layer; and

a top-gate electrode formed over the top-gate dielectric layer.

12. A device, comprising:

a substrate including a first surface contour defined by a first region and a second region adjacent to and on either side of the first region, wherein the first region includes a curved region and wherein the second region includes a substantially planar region;

an insulating layer formed over the first and second regions of the substrate, wherein the insulating layer includes a second surface contour that conforms to the first surface contour of the substrate;

a graphene layer formed over the insulating layer, wherein the graphene layer includes a third surface contour that conforms to the second surface contour of the insulating layer, wherein the graphene layer over the first region includes a curved graphene layer, and wherein the graphene layer over the second region includes a substantially planar graphene layer; and

source and drain electrodes in contact with the graphene layer in the second region.

13. The device of claim 12, further comprising:

a top-gate dielectric layer formed over the graphene layer in the first region; and

a top-gate electrode formed over the top-gate dielectric layer.

14. The device of claim 12, wherein the curved region includes one of a concave region and a convex region.

15. The device of claim 12, wherein the graphene layer includes one of monolayer graphene, bilayer graphene, and multi-layer graphene.

16. The device of claim 12, wherein the first region includes a channel region of the device.

17. The device of claim 16, wherein the graphene layer is semiconducting within the channel region, and wherein the graphene layer is metallic beneath the source and drain electrodes.

18. A semiconductor device, comprising:

a substrate including a nanorod, wherein the nanorod includes an insulating outer surface that traverses a circumference of the nanorod; and

a carbon nanotube (CNT) disposed on the insulating outer surface of the nanorod;

wherein the nanorod includes a first diameter, wherein the CNT includes a second diameter substantially equal to the first diameter, and wherein a CNT band gap is determined at least in part by the first diameter.

19. The semiconductor device of claim 18, wherein the CNT includes one of a single-wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT).

20. The semiconductor device of claim 18, wherein the nanorod includes a metallic nanorod, a semiconducting nanorod, or an insulating nanorod.