METHODS AND APPARATUS FOR AN ENCODER

• US 20190271961A1
• Filed: 03/01/2018
• Published: 09/05/2019
• Est. Priority Date: 03/01/2018
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: NERAYANURU, Sreenivasa Murthy, Allgood, Jeffrey Dennis
• Granted Patent: US 10,642,243 B2
• Time in Patent Office: Days
• CPC Class Codes: G05B 19/401 characterised by control arrangements for measuring, e.g. calibration and initialisation, measuring workpiece for machining purposes G05B19/19 takes precedence
• CPC Class Codes: G05B 2219/37154 Encoder and absolute position counter
• CPC Class Codes: G05B 2219/37155 Encoder and delta position counter
• CPC Class Codes: G06F 17/141 Discrete Fourier transforms
• CPC Class Codes: G06F 7/5446 using crossaddition algorithms, e.g. CORDIC
• CPC Class Codes: H02K 11/22 Optical devices

Abstract

Various embodiments of the present technology comprise a method and apparatus for an encoder. In various embodiments, the encoder is configured to remove impairments from the signals produced by a servo motor and compute a phase that is used to determine the rotary position of the servo motor. In various embodiments, the encoder is configured to remove a DC offset, improve amplitude mismatch, and compute a phase offset.

Claims

1. An integrated circuit capable of receiving a first input signal and a second input signal, comprising:

a first filter configured to compute a first quadrature of the first input signal;

a second filter configured compute a second quadrature of the second input signal;

a first phase estimation circuit coupled to an output terminal of the first filter and configured to estimate a first phase according to the first input signal and the first quadrature;

a second phase estimation circuit coupled to an output terminal of the second filter and configured to estimate a second phase according to the second input signal and the second quadrature; and

a phase offset circuit coupled to the output terminals of the first and second phase estimation circuits and configured to compute a phase offset based on the first and second phases.

2. The integrated circuit according to claim 1, further comprising a first correction circuit configured to:

apply a fixed gain to the first and second input signals; and

apply a coarse DC offset correction to the first and second input signals.

3. The integrated circuit according to claim 2, further comprising a second correction circuit coupled to an output terminal of the first correction circuit and configured to:

apply a dynamic gain to the first and second input signals; and

apply a fine DC offset correction to the first and second input signals.

4. The integrated circuit according to claim 3, wherein the second correction circuit comprises:

a peak and valley detection circuit configured to compute a peak and a valley of each of the first and second channel data;

an offset correction circuit coupled to the peak and valley detection circuit and configured to apply the second DC offset correction; and

a gain correction circuit coupled to the offset correction circuit, and configured to apply the second gain correction according to an ideal peak signal.

5. The integrated circuit according to claim 1, further comprising a decimator configured to change a sampling rate of the first and second input signal.

6. The integrated circuit according to claim 1, wherein:

the first and second phase estimation circuits utilize a Coordinate Rotation Digital Computer (CORDIC) algorithm to compute the first and second phases; and

each of the first and second filters comprise Discrete Hilbert Transform filters.

7. The integrated circuit according to claim 1, further comprising:

a first delay circuit coupled in parallel with the first filter and configured to apply a time delay to the first input signal; and

a second delay circuit coupled in parallel with the second filter and configured to apply the time delay to the second input signal.

8. The integrated circuit according to claim 1, computing a final phase according to the phase offset, the first phase, and a frequency.

9. The integrated circuit according to claim 8, wherein the integrated circuit is further configured to compute a motor position according to the final phase.

10. A method for computing a motor position, comprising:

decimating a first input signal and a second input signal;

computing a first quadrature of the first signal;

computing a second quadrature of the second input signal;

computing a first phase according to at least one of;

the first input signal and the first quadrature;

computing a second phase according to at least one of;

the second input signal and the second quadrature;

computing a phase offset based on the computed first and second phases; and

computing the motor position based on the phase offset, the first phase, and a frequency.

11. The method according to claim 10, further comprising:

correcting a DC offset of the first and second input signals;

applying a fixed gain to the first and second input signals; and

applying a dynamic gain to the first and second input signals.

12. The method according to claim 10, further comprising applying a time delay to each of the first and second input signals.

13. The method according to claim 10, further comprising computing a frequency of the each of the first and second input signals.

14. The method according to claim 10, further comprising removing a time delay from the phase offset.

15. A system capable of generating a first signal and a second signal, comprising:

a motor assembly comprising;

a motor having a motor position; and

an optical encoder coupled to the motor and comprising;

a first correction circuit configured to;

apply a first gain to the first and second signals;

apply a first DC offset correction to the first and second signals;

generate first channel data; and

generate second channel data;

a second correction circuit coupled to an output terminal of the first correction circuit and configured to;

apply a second gain to the first and second channel data;

apply a second DC offset correction to the first and second channel data;

generate corrected first channel data; and

generate corrected second channel data;

a signal processing circuit coupled to the second correction circuit and configured to;

compute a first quadrature of the first signal;

compute a second quadrature of the second signal;

estimate a first phase according to the first signal and the first quadrature;

estimate a second phase according to the second signal and the second quadrature; and

compute a phase offset based on the first and second phases.

16. The system according to claim 15, wherein:

the first gain comprises a fixed gain; and

the second gain comprises a dynamic gain.

17. The system according to claim 15, wherein:

the first DC offset correction comprises a coarse correction; and

the second DC offset correction comprises a fine correction.

18. The system according to claim 15, wherein the optical encoder circuit further comprises a decimator coupled between the output terminal of the second correction circuit and the signal processing circuit, and configured to change a sampling rate of the first and second channel data.

19. The system according to claim 15, wherein the system is further configured to compute:

a final phase according to the phase offset, the first phase, and a frequency; and

the motor position according to the final phase.

20. The system according to claim 15, wherein the second correction circuit comprises:

a peak and valley detection circuit configured to compute a peak and a valley of each of the first and second channel data;

an offset correction circuit coupled the peak and valley detection circuit and configured to apply the second DC offset correction; and

a gain correction circuit coupled to the offset correction circuit, and configured to apply the second gain correction according to an ideal peak signal.