SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY

• US 20190279722A1
• Filed: 02/13/2019
• Published: 09/12/2019
• Est. Priority Date: 06/17/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Granted Patent: US 10,643,714 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Claims

1. (canceled)

2. A memory array, comprising:

multiple strings of vertically arranged memory cells, each memory cell including a charge storage structure, each memory string extending between a source and a respective bit line of multiple bit lines, wherein the bit lines extend in a first direction;

a first group of memory cell strings each selectively coupled to a first bit line through a respective select device in each memory cell string;

a second group of memory cell strings each selectively coupled to a second bit line through a respective select device in each memory cell string, wherein the second bit line is stacked above the first bit line, and wherein the first and second groups of memory cell strings are interleaved with one another along the first direction in which the first and second bit lines extend;

access lines coupled to respective memory cells in each of the first and second groups of memory cell strings, each access line configured to allow access to a respective memory cell in each of the first and second groups of memory cell strings to perform a memory operation involving such memory cell;

a memory controller configured to perform a shielded bit line sensing operation, in which the first bit line is coupled to a shield potential during at least a portion of sensing interval in which the state of a selected memory cell in a selected memory cell string of the second group of memory cell strings is sensed, and wherein during the sensing interval the selected memory cell is coupled to the second bit line.

3. The memory array of claim 2, further comprising:

a third group of memory cell strings each selectively coupled to a third bit line through a respective select device in each memory cell string of the third group, wherein the third bit line is stacked above the second bit line; and

a fourth group of memory cell strings each selectively coupled to a fourth bit line through a respective select device in each memory cell string of the fourth group, wherein the fourth bit line is stacked above the third bit line;

wherein four adjacent memory cell strings along the direction of the bit lines are selectively coupled to one of the first, second, third, and fourth bit lines and

wherein the memory controller is further configured to couple the first and third bit lines to a shield potential during at least a portion of the sensing of the selected memory cell in the selected memory cell string coupled to the second bit line.

4. The memory array of claim 3, wherein the memory controller is further configured to apply a read voltage to the second bit line during a first interval in the sensing the state of the selected memory cell, and to couple the first and third bit lines to a shield potential during at least a portion of the first interval.

5. The memory array of claim 3, wherein the controller is configured to couple the third data line coupled to the third group of memory cell strings to the shield potential during at least a portion of a second sensing of a state of a second selected memory cell of a second selected memory string within the fourth group of memory cell strings.

6. The memory array of claim 3, wherein the second and fourth bit lines are selected during sensing of the selected memory cell, and wherein the first and third bit lines are unselected during the selected memory cell sensing.

7. The memory array of claim 5, wherein the unselected bit lines are coupled to a ground potential during the selected memory cell sensing.

8. The memory array of claim 2, wherein the first bit line and the second bit line are selectively coupled to a common page buffer through first and second bit line transfer devices, respectively.

9. A method of operating a memory array having multiple vertical strings of memory cells, comprising:

accessing selected memory cells from the multiple strings of memory cells,

wherein the multiple strings of memory cells are arranged in rows and columns, each string having multiple vertically arranged memory cells and extending between a source and a respective bit line of multiple bit lines,

wherein the bit lines extend in a first direction, and wherein first and second bit lines are vertically stacked relative to one another,

wherein strings of memory cells that are adjacent to one another along the first direction are coupled to different bit lines,

wherein the vertically arranged memory cells of the multiple strings are associated with respective access lines, and

wherein the access lines are coupled to respective memory cells in each of a plurality of strings of the multiple strings;

applying a pass voltage to access lines not associated with the selected memory cells;

applying an operational voltage to a selected access line associated with the selected memory cells to enable the selected memory cells;

coupling a first bit line of the multiple stacked bit lines to a shield voltage line during at least a portion of a memory operation; and

wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second bit line during the memory operation, and

wherein strings of memory cells that do not contain the enabled memory cells are operably coupled to the first bit line during at least a portion of the memory operation.

10. The method of claim 9, wherein the operational voltage Is a sense voltage.

11. The method of claim 9, wherein the shield voltage is ground potential.

12. The method of claim 11, further comprising enabling select gate drain and select gate source transistors that are coupled to strings of memory cells comprising the enabled memory cells.

13. The method of claim 12, further comprising enabling storing data from selected memory cells in page buffers.

14. The method of claim 9, further comprising disabling select gate drain and select gate source transistors that are coupled to strings of memory cells that do not include the enabled memory cells.

15. The method of claim 9, wherein the operational voltage is a program voltage.

16. The method of claim 10, further comprising applying a ground voltage to the shield voltage line when the operational voltage is a sense voltage.

17. The method of claim 15, further comprising applying a positive voltage to the shield voltage line when the operational voltage is a program voltage.

18. The method of claim 9, wherein the memory array is a block of vertical strings of memory cells, wherein all strings of the block are selectively coupled to a common source.

19. A method, comprising:

operating a memory array having multiple strings of memory cells,

wherein each memory cell string extends vertically and includes multiple vertically arranged memory cells and extends between a source and a respective bit line of multiple bit lines,

wherein the multiple bit lines extend in a first direction, and include a first group of bit lines and a second group of bit lines, wherein the bit lines of the second group are vertically stacked relative to respective bit lines of the first group,

wherein strings of memory cells that are adjacent one another along the first direction are coupled to different bit lines,

wherein the vertically arranged memory cells of the memory cell strings are associated with a respective access line,

wherein the access lines are coupled to respective memory cells in each of multiple strings, and

wherein the multiple memory cell strings are selectively coupled to a respective bit line through a respective select gate drain transistor;

the operating of the memory array comprising,

applying a read voltage to a selected access line of multiple access lines, each access line coupled to a respective memory cell in each string of a first group of strings of memory cells;

applying a read pass voltage to unselected access lines of the multiple access lines;

applying a pre-charge voltage to a first group of bit lines during a read operation;

applying a shield voltage to a second group of bit lines during at least a portion of the read operation; and

applying an enable voltage to select gate drain transistors of a second group of memory cell strings comprising the enabled memory cells to couple the second group of memory cell strings to respective bit lines of the second group of bit lines during the read operation.

20. The method of claim 19, wherein the memory array is a block of NAND memory cells.

21. The method of claim 20, wherein the first group of bit lines are coupled to respective first bit line shield transistors, and wherein the method further comprises applying a disable voltage to control gates of the first data line shield transistors such that the first group of data lines are not operably coupled to the shield voltage line.

22. The method of claim 21, wherein the second group of data lines are coupled to respective second bit line shield transistors, and wherein applying a shield voltage to the second group of bit lines comprises applying an enable voltage to control gates of the second data line shield transistors such that the second group of data lines are coupled to the shield voltage line.