METHODS, APPARATUS, AND SYSTEM FOR REDUCING GATE CUT GOUGING AND/OR GATE HEIGHT LOSS IN SEMICONDUCTOR DEVICES

• US 20190280114A1
• Filed: 03/12/2018
• Published: 09/12/2019
• Est. Priority Date: 03/12/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Gao, Jinsheng, Jaeger, Daniel, Aquilino, Michael, Carpenter, Patrick, Wu, Xusheng, Huang, Haigou
• Granted Patent: US 10,644,156 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Claims

1. A method, comprising:

forming a fin disposed on a semiconductor substrate;

forming a dummy gate disposed over said fin, wherein said dummy gate has a top at a first height above said substrate;

forming an interlayer dielectric (ILD) feature disposed over said fin and adjacent said dummy gate, wherein said ILD has a top at a second height above said substrate, and wherein the second height is below the first height; and

capping said ILD with a dielectric cap, wherein the dielectric cap has a top at the first height.

2. The method of claim 1, wherein forming said ILD feature comprises forming the ILD to have the top at the first height and recessing the top of the ILD to the second height.

3. The method of claim 1, wherein capping said ILD with a dielectric cap comprises capping said ILD with a dielectric cap that comprises silicon carbon oxide (SiOC).

4. The method of claim 3, wherein capping said ILD comprises depositing SiOC over the semiconductor structure, depositing an oxide over the SiOC, chemical-mechanical polishing (CMP) the oxide and the SiOC to the first height, and performing a non-selective etch to remove oxide.

5. The method of claim 1, further comprising:

replacing said dummy gate with a gate stack comprising a metal gate electrode and a nitride cap;

removing said dielectric cap and the ILD, to yield a trench; and

filling said trench with a contact metal.

6. The method of claim 5, wherein the contact metal is selected from the group consisting of tungsten, copper, and cobalt.

7. The method of claim 5, wherein filling the trench with the contact metal comprises overfilling the trench with the contact metal and performing CMP to reduce a top of the contact metal to the first height.

8. The method of claim 5, wherein replacing said dummy gate with said gate stack comprises forming the gate stack such that the top of the dielectric cap is less than 5 nm below the top of the nitride cap.

9. A semiconductor device, comprising:

a semiconductor substrate;

a fin disposed on the semiconductor substrate;

a gate stack disposed over the fin, wherein the gate stack has a top and sidewalls;

an interlayer dielectric (ILD) adjacent one of the sidewalls of the gate, wherein the ILD has a top; and

a dielectric cap disposed on the top of the ILD, wherein the dielectric cap has a top, and the top of the dielectric cap is substantially coplanar with the top of the gate.

10. The semiconductor device of claim 9, wherein the top of the dielectric cap is less than 5 nm below the top of the gate stack.

11. The semiconductor device of claim 9, wherein the semiconductor device is formed by a method comprising:

providing a semiconductor substrate;

a fin disposed on the semiconductor substrate;

a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and

an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and

capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height.

12. The semiconductor device of claim 11, wherein the dielectric cap comprises silicon carbon oxide (SiOC).

13. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to;

provide a semiconductor substrate;

a fin disposed on the semiconductor substrate;

a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and

an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and

cap the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height.

14. The system of claim 13, wherein the semiconductor device processing system is adapted to provide the semiconductor structure by forming the ILD to have the top at the first height and recessing the top of the ILD to the second height.

15. The system of claim 13, wherein the semiconductor device processing system is adapted to form the dielectric cap from silicon carbon oxide (SiOC).

16. The system of claim 15, wherein the semiconductor device processing system is adapted to cap the ILD by depositing SiOC over the semiconductor structure, depositing an oxide over the SiOC, chemical-mechanical polishing (CMP) the oxide and the SiOC to the first height, and performing a non-selective etch to remove oxide.

17. The system of claim 13, wherein the semiconductor device processing system is further adapted to:

replace the dummy gate with a gate stack comprising a metal gate electrode and a nitride cap;

remove the dielectric cap and the ILD, to yield a trench; and

fill the trench with a contact metal.

18. The system of claim 17, wherein the semiconductor device processing system is adapted to form the contact metal from tungsten or cobalt.

19. The system of claim 17, wherein the semiconductor device processing system is adapted to fill the trench with the contact metal by overfilling the trench with the contact metal and performing CMP to reduce a top of the contact metal to the first height.

20. The system of claim 17, wherein, after the semiconductor device processing system replaces the dummy gate with the gate stack, the top of the dielectric cap is less than 5 nm below the top of the nitride cap.