CLOCK AND DATA RECOVERY CIRCUIT

• US 20190280696A1
• Filed: 09/24/2018
• Published: 09/12/2019
• Est. Priority Date: 03/07/2018
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: WANG, Chien-Chung, WENG, Meng-Tse
• Granted Patent: US 10,615,804 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.

Claims

1. A clock and data recovery circuit, comprising:

a first phase detector, comparing a phase of a data signal with that of a first clock signal to output a first output signal, wherein the first output signal indicates whether the phase of data signal is ahead or behind that of the first clock signal;

an auxiliary module, comprising;

an auxiliary clock generator, generating an auxiliary clock signal;

a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of the first clock signal to output a second output signal, wherein the second output signal indicates whether the phase of the auxiliary clock signal is ahead or behind that of the first clock signal; and

a multiplexing selecting unit, coupled to the first phase detector and the second phase detector, outputting a multiplexing output signal according to a selection signal;

a first charge pump, coupled to the multiplexing selecting unit, outputting a control signal according to the multiplexing output signal; and

a first voltage-controlled oscillator (VCO), coupled to the first charge pump, generating the first clock signal according to the control signal;

wherein the second phase detector comprises;

a first delay unit, receiving the auxiliary clock signal and the first clock signal to generate a first delayed signal;

a second delay unit, coupled to the first delay unit, receiving the first delayed signal and the first clock signal to generate a second delayed signal;

a first exclusive OR (XOR) gate, performing an XOR operation on the auxiliary clock signal and the first delayed signal to generate a first rising signal; and

a second XOR gate, performing an XOR operation on the first delayed signal and the second delayed signal to generate a first falling signal;

wherein, the first rising signal and the first falling signal form the second output signal.

3. The clock and data recovery circuit according to claim 1, wherein the first phase detector comprises:

a third delay unit, receiving the data signal and the first clock signal to generate a third delayed signal;

a forth delay unit, coupled to the third delay unit, receiving the third delayed signal and the first clock signal to generate a fourth delayed signal;

a third XOR gate, performing an XOR operation on the data signal and the third delayed signal to generate a second rising signal; and

a fourth XOR gate, performing an XOR operation on the third delayed signal and the fourth delayed signal to generate a second falling signal;

wherein the second rising signal and the second falling signal form the first output signal.

4. The clock and data recovery circuit according to claim 3, wherein the multiplexing selecting unit comprises:

a first multiplexer, receiving the first rising signal and the second rising signal, and outputting a third rising signal according to the selection signal; and

a second multiplexer, receiving the first falling signal and the second falling signal, and outputting a third falling signal according to the selection signal;

wherein, the third rising signal and the third falling signal form the multiplexing output signal.

5. The clock and data recovery circuit according to claim 4, wherein the first charge pump comprises:

a capacitor, outputting the control signal;

a first switch, having one end thereof receiving a first voltage and one other end thereof coupled to the capacitor, the first switch controlled by the third rising signal; and

a second switch, having one end thereof receiving a second voltage and one other end thereof coupled to the capacitor, the second switch controlled by the third falling signal.

6. The clock and data recovery circuit according to claim 5, wherein the first switch is a first transistor, the second switch is a second transistor, the first voltage is a positive voltage, and the second voltage is a ground voltage.

10. The clock and data recovery circuit according to claim 1, wherein the multiplexing selecting unit is coupled to a control circuit, which generates the selection signal.

11. The clock and data recovery circuit according to claim 1, further comprising another phase frequency detector, which is coupled to the first VCO and receives a reference clock signal.

12. The clock and data recovery circuit according to claim 1, further comprising a phase detector, which is coupled to the first VCO.

2. (canceled)

7. A clock and data recovery circuit, comprising:

a first phase detector, comparing a phase of a data signal with that of a first clock signal to output a first output signal, wherein the first output signal indicates whether the phase of data signal is ahead or behind that of the first clock signal;

an auxiliary module, comprising;

an auxiliary clock generator, generating an auxiliary clock signal;

a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of the first clock signal to output a second output signal, wherein the second output signal indicates whether the phase of the auxiliary clock signal is ahead or behind that of the first clock signal; and

a multiplexing selecting unit, coupled to the first phase detector and the second phase detector, outputting a multiplexing output signal according to a selection signal;

a first charge pump, coupled to the multiplexing selecting unit, outputting a control signal according to the multiplexing output signal; and

a first voltage-controlled oscillator (VCO), coupled to the first charge pump, generating the first clock signal according to the control signal;

wherein the auxiliary clock generator comprises;

a phase frequency detector, receiving an input clock signal;

a second charge pump, coupled to the phase frequency detector; and

a second VCO, coupled between the second charge pump and the phase frequency detector, generating the auxiliary clock signal.

8. The clock and data recovery circuit according to claim 7, wherein the auxiliary clock generator further comprises:

a frequency divider, coupled between the second VCO and the phase frequency detector, generating a frequency dividing signal according to the auxiliary clock signal; and

wherein, the phase frequency detector receives the frequency dividing signal.

9. The clock and data recovery circuit according to claim 7, wherein the auxiliary clock generator further comprises:

a low-pass filter (LPF), coupled between the second charge pump and the second VCO.