DELAY CIRCUIT
First Claim
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1. A delay circuit comprising:
- a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal;
a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock;
a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and
a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.
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Abstract
A delay circuit includes: a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.
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Citations
14 Claims
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1. A delay circuit comprising:
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a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory system comprising:
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a memory device; and a memory controller including a delay circuit, wherein the delay circuit includes; a variable delay line suitable for receiving a data strobe signal as an input signal from the memory device and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification