DELAY CIRCUIT

• US 20190280697A1
• Filed: 11/20/2018
• Published: 09/12/2019
• Est. Priority Date: 03/07/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: JUNG, In-Hwa
• Granted Patent: US 10,644,707 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A delay circuit includes: a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.

Claims

1. A delay circuit comprising:

a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal;

a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock;

a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and

a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.

2. The delay circuit of claim 1, wherein the first and second clocks have a phase difference corresponding to a target delay value of the variable delay line.

3. The delay circuit of claim 2, wherein the control circuit increases the delay value of the variable delay line when the phase difference between the input signal and the first clock is greater than the phase difference between the output signal and the second clock, and decreases the delay value of the variable delay line when the phase difference between the output signal and the second clock is greater than the phase difference between the input signal and the first clock.

4. The delay circuit of claim 2, wherein each of the first and second phase difference detectors comprises a time-to-digital converter.

5. The delay circuit of claim 2, wherein the first phase difference detector comprises:

first to Mth delay lines coupled in series and suitable for generating first to Mth clocks respectively by sequentially delaying the first clock, where M is an integer greater than or equal to 2; and

first to Mth D flip-flops suitable for sampling the input signal in synchronization with the corresponding clocks among the first to Mth clocks,

wherein the detection result of the first phase difference detector is outputted through output terminals of the first to Mth D flip-flops.

6. The delay circuit of claim 2, wherein the second phase difference detector comprises:

first to Mth second delay lines coupled in series and suitable for generating first to Mth clocks respectively by sequentially delaying the second clock, where M is an integer greater than or equal to 2; and

first to Mth D flip-flops suitable for sampling the output signal in synchronization with the corresponding clocks among the first to Mth clocks,

wherein the detection result of the second phase difference detector is outputted through output terminals of the first to Mth D flip-flops.

7. The delay circuit of claim 2, wherein the input signal comprises a periodic wave.

8. A memory system comprising:

a memory device; and

a memory controller including a delay circuit,

wherein the delay circuit includes;

a variable delay line suitable for receiving a data strobe signal as an input signal from the memory device and generating an output signal by delaying the input signal;

a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock;

a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and

a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.

9. The memory system of claim 8, wherein the first and second clocks have a phase difference corresponding to a target delay value of the variable delay line.

10. The memory system of claim 9, wherein the control circuit increases the delay value of the variable delay line when the phase difference between the input signal and the first clock is greater than the phase difference between the output signal and the second clock, and decreases the delay value of the variable delay line when the phase difference between the output signal and the second clock is greater than the phase difference between the input signal and the first clock.

11. The memory system of claim 9, wherein each of the first and second phase difference detectors comprises a time-to-digital converter.

12. The memory system of claim 9, wherein the first phase difference detector comprises:

first to Mth delay lines coupled in series and suitable for generating first to Mth clocks respectively by sequentially delaying the first clock, where M is an integer greater than or equal to 2; and

first to Mth D flip-flops suitable for sampling the input signal in synchronization with the corresponding clocks among the first to Mth clocks,

wherein the detection result of the first phase difference detector is outputted through output terminals of the first to Mth D flip-flops.

13. The memory system of claim 9, wherein the second phase difference detector comprises:

first to Mth second delay lines coupled in series and suitable for generating first to Mth clocks respectively by sequentially delaying the second clock, where M is an integer greater than or equal to 2; and

first to Mth D flip-flops suitable for sampling the output signal in synchronization with the corresponding clocks among the first to Mth clocks,

wherein the detection result of the second phase difference detector is outputted through output terminals of the first to Mth D flip-flops.

14. The memory system of claim 9, wherein the input signal comprises a periodic wave.