MEMORY DECISION FEEDBACK EQUALIZER BIAS LEVEL GENERATION
First Claim
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1. A device, comprising:
- a selection circuit configured to generate a bias level, wherein the selection circuit comprises a receiver coupled to an operational amplifier, wherein the operational amplifier is configured to transmit an output to an input of the receiver to adjust the bias level;
a combinational circuit coupled to the selection circuit and configured to generate a distortion correction factor used to offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal; and
a data latch coupled to the combinational circuit and configured to receive the correction signal to generate a corrected bit.
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Abstract
A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.
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Citations
20 Claims
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1. A device, comprising:
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a selection circuit configured to generate a bias level, wherein the selection circuit comprises a receiver coupled to an operational amplifier, wherein the operational amplifier is configured to transmit an output to an input of the receiver to adjust the bias level; a combinational circuit coupled to the selection circuit and configured to generate a distortion correction factor used to offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal; and a data latch coupled to the combinational circuit and configured to receive the correction signal to generate a corrected bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A device, comprising:
an equalizer, comprising; a first input configured to receive distorted input data as part of a data stream; and a summer circuit configured to apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, wherein the summer circuit comprises a controllable source configured to supply a current, wherein the controllable source comprises a current source controlled by a bias level to generate the current, wherein the summer circuit is configured to receive and utilize a first weighted tap value to apply the current to the distorted input data as at least a portion of the correction factor. - View Dependent Claims (12, 13, 14, 15)
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16. A device, comprising:
an equalizer, comprising; a first input configured to receive distorted input data as part of a data stream; a second input configured to receive a reference signal; and a summer circuit, comprising; a first controllable source configured to supply a first current, wherein the first controllable source comprises a first current source controlled by a bias level to generate the first current, wherein the summer circuit is configured to receive and utilize a first weighted tap value to apply the first current to the distorted input data to generate modified input data; and a second controllable source configured to supply a second current, wherein the second controllable source comprises a second current source controlled by a second bias level to generate the second current, wherein the summer circuit is configured to receive and utilize a second weighted tap value to apply the second current to the reference signal to generate a modified reference signal, wherein the first weighted tap value and the second weighted tap value are selected to offset inter-symbol interference from the data stream on the distorted input data. - View Dependent Claims (17, 18, 19, 20)
Specification