Low-pincount High-bandwidth Memory And Memory Bus
First Claim
1. An integrated circuit (IC) primarily adapted for memory storage (Memory IC), comprising:
- a plurality of sets of bus connection terminals adapted to be electrically coupled to corresponding functional terminals on a Controller IC via a collection of electrical bus conductors,wherein a first set of the bus connection terminals of the Memory IC is configured to receive, during a command transfer time, a parallel command from the Controller IC through one or more bus conductors in a data bus group, and is further adapted to transport data between the memory IC and the controller IC using a burst mode during a data transfer time, andwherein a second set of the bus connection terminals of the Memory IC is configured to receive, from the controller IC through a single conductor, a serial command during the data transfer time such that the serial command can direct the operation of the Memory IC by providing address and data transfer control information to the Memory IC.
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Accused Products
Abstract
A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.
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Citations
21 Claims
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1. An integrated circuit (IC) primarily adapted for memory storage (Memory IC), comprising:
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a plurality of sets of bus connection terminals adapted to be electrically coupled to corresponding functional terminals on a Controller IC via a collection of electrical bus conductors, wherein a first set of the bus connection terminals of the Memory IC is configured to receive, during a command transfer time, a parallel command from the Controller IC through one or more bus conductors in a data bus group, and is further adapted to transport data between the memory IC and the controller IC using a burst mode during a data transfer time, and wherein a second set of the bus connection terminals of the Memory IC is configured to receive, from the controller IC through a single conductor, a serial command during the data transfer time such that the serial command can direct the operation of the Memory IC by providing address and data transfer control information to the Memory IC. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory storage integrated circuit (Memory IC), configured for being interconnected to a controller IC via a bus, wherein the Memory IC is adapted to receive commands and transfer data through common connection terminals, and wherein a single connection terminal of the Memory IC, not used for transporting data during data transfer, is adapted to receive a serial command from the controller IC concurrent with the data transfer, such that the serial command can direct the operation of the Memory IC by providing address and data transfer control information to the Memory IC.
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13. A memory storage integrated circuit (Memory IC), comprising:
means for receiving, during a data transfer time, a serial command from a Controller IC via a single conductor of a bus coupled to a single terminal on the Memory IC not used to transport data, the serial command directing operation of the Memory IC, by providing address and data transfer control means to the Memory IC. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
Specification