REFERENCE SIGNAL AND CONTROL INFORMATION PROCESSING IN 5G-NR WIRELESS SYSTEMS

• US 20190306923A1
• Filed: 06/19/2019
• Published: 10/03/2019
• Est. Priority Date: 06/19/2018
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel Corporation
• Inventors: Xiong, Gang, Zhang, Yushu, Lee, Dae Won, Davydov, Alexei Vladimirovich, Han, Seunghee, Zhu, Jie, Belov, Dmitry, Chatterjee, Debdeep, Chervyakov, Andrey, Hamidi-Sepehr, Fatemeh, He, Hong, Islam, Toufiqul, Jeon, Jeongho, Khoryaev, Alexey Vladimirovich, Kundu, Lopamudra, Kwak, Yongjun, Oviedo, Jose Armando, Panteleev, Sergey, Shilov, Mikhail, Sosnin, Sergey, Talarico, Salvatore, Zaleski, Jan
• Granted Patent: US 11,432,369 B2
• Time in Patent Office: Days
• CPC Class Codes: H04J 13/0062 Zadoff-Chu
• CPC Class Codes: H04J 2011/0006 with CDM/CDMA
• CPC Class Codes: H04L 27/2607 Cyclic extensions
• CPC Class Codes: H04L 27/261 Details of reference signals
• CPC Class Codes: H04L 27/2636 with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
• CPC Class Codes: H04L 5/0005 Time-frequency
• CPC Class Codes: H04L 5/0051 of dedicated pilots, i.e. pilots destined for a single user or terminal
• CPC Class Codes: H04L 5/0091 Signaling for the administration of the divided path
• CPC Class Codes: H04W 72/23 in the downlink direction of a wireless link, i.e. towards a terminal
• CPC Class Codes: H04W 76/27 Transitions between radio resource control [RRC] states
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals

Abstract

A user equipment (UE) can include processing circuitry coupled to memory. To configure the UE for New Radio (NR) communications above a 52.6 GHz carrier frequency, the processing circuitry is to decode radio resource control (RRC) signaling to obtain a cyclic shift value in time domain. The cyclic shift value is associated with a demodulation reference signal (DM-RS) antenna port (AP) of a plurality of available DM-RS APs. A single carrier based waveform DM-RS sequence corresponding to the DM-RS AP is generated using a base sequence and the cyclic shift value. The single carrier based waveform DM-RS sequence is encoded with uplink data for transmission to a base station using a physical uplink shared channel (PUSCH) using a carrier above the 52.6 GHz carrier frequency.

Claims

1. An apparatus of a user equipment (UE), the apparatus comprising:

processing circuitry, wherein to configure the UE for New Radio (NR) communications above a 52.6 GHz carrier frequency, the processing circuitry is to;

decode radio resource control (RRC) signaling to obtain a cyclic shift value in time domain, the cyclic shift value associated with a demodulation reference signal (DM-RS) antenna port (AP) of a plurality of available DM-RS APs;

generate a single carrier based waveform DM-RS sequence corresponding to the DM-RS AP using a base sequence and the cyclic shift value; and

encode the single carrier based waveform DM-RS sequence with uplink data for transmission to a base station using a physical uplink shared channel (PUSCH) using a carrier above the 52.6 GHz carrier frequency; and

memory coupled to the processing circuitry, the memory configured to store the cyclic shift value.

2. The apparatus of claim 1, wherein the base sequence is one of a Zadoff-Chu sequence or a computer-generated sequence (CGS).

3. The apparatus of claim 1, wherein the single carrier based waveform DM-RS sequence is a single carrier with frequency domain equalizer (SC-FDE) DM-RS sequence generated according to the following equation:

y(n)=r_u,v((n+L) mod N_ZC), n=0, 1, . . . , N, where r_u,v(n) is the base sequence, N_ZC is the base sequence length, L is the cyclic shift value, N is the base sequence length, u is a group number, and v is a number of the base sequence within the group.

4. The apparatus of claim 1, wherein the processing circuitry is to:

insert a guard interval (GI) sequence before and after the DM-RS sequence within a single carrier with frequency domain equalizer (SC-FDE) block, wherein the GI sequence is independently generated from the DM-RS sequence.

5. The apparatus of claim 1, wherein the processing circuitry is to:

insert a guard interval (GI) sequence before the DM-RS sequence within a single carrier with frequency domain equalizer (SC-FDE) block, wherein a length of the DM-RS sequence equals a Fast Fourier Transform (FFT) size and the GI sequence is a portion of the DM-RS sequence.

6. The apparatus of claim 1, wherein the processing circuitry is to:

apply a hopping pattern to the base sequence, wherein the hopping pattern is initialized using at least one of the following;

a slot index, a single carrier with frequency domain equalizer (SC-FDE) block index, a SC-FDE sub-block index, or a configurable ID.

7. The apparatus of claim 1, wherein the processing circuitry is to:

apply a block-wised orthogonal cover code (OCC) to the DM-RS sequence in time domain to generate a block-wised spread DM-RS sequence, the block-wised spread DM-RS sequence associated with one of the plurality of available DM-RS APs.

8. The apparatus of claim 7, wherein the block-wised OCC is applied on a block level or a sub-block level.

9. The apparatus of claim 7, wherein the processing circuitry is to:

decode downlink control information (DCI) indicating an AP for use during the uplink data transmission;

generate the block-wised spread DM-RS sequence based on the indicated AP; and

encode the block-wised spread DM-RS sequence with the uplink data for transmission to the base station using the PUSCH.

10. The apparatus of claim 1, further comprising transceiver circuitry coupled to the processing circuitry;

and, one or more antennas coupled to the transceiver circuitry.

11. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of a base station operating in a 5G network, the instructions to configure the one or more processors for New Radio (NR) communications above a 52.6 GHz carrier frequency and to cause the base station to:

encode radio resource control (RRC) signaling with a cyclic shift value in time domain for transmission to a user equipment (UE), the cyclic shift value associated with a demodulation reference signal (DM-RS) antenna port (AP) of a plurality of available DM-RS APs;

decode a single carrier based waveform DM-RS sequence corresponding to the DM-RS AP, the DM-RS sequence received from the UE with uplink data via a physical uplink shared channel (PUSCH) using a carrier above the 52.6 GHz carrier frequency;

determine a channel estimate of the PUSCH using the DM-RS sequence; and

decode the uplink data based on the channel estimate;

wherein the DM-RS sequence is a single carrier based waveform DM-RS sequence generated using a base sequence and the cyclic shift value; and

encode the single carrier based waveform DM-RS sequence with uplink data for transmission to a base station using a physical uplink shared channel (PUSCH); and

memory coupled to the processing circuitry, the memory configured to store the cyclic shift value.

12. The non-transitory computer-readable storage medium of claim 11, wherein the base sequence is one of a Zadoff-Chu sequence or a computer-generated sequence (CGS).

13. The non-transitory computer-readable storage medium of claim 11, wherein the single carrier based waveform DM-RS sequence is a single carrier with frequency domain equalizer (SC-FDE) DM-RS sequence generated according to the following equation:

y(n)=fr_u,v((n+L) mod N_ZC), n=0, 1, . . . , N, where r_u,v(n) is the base sequence, N_ZC is the base sequence length, L is the cyclic shift value, N is the base sequence length, u is a group number, and v is a number of the base sequence within the group.

14. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of a user equipment (UE), the instructions to configure the one or more processors for New Radio (NR) communications above a 52.6 GHz carrier frequency and to cause the UE to:

decode radio resource control (RRC) signaling to obtain a cyclic shift value in time domain, the cyclic shift value associated with a demodulation reference signal (DM-RS) antenna port (AP) of a plurality of available DM-RS APs;

generate a single carrier based waveform DM-RS sequence corresponding to the DM-RS AP using a base sequence and the cyclic shift value; and

encode the single carrier based waveform DM-RS sequence with uplink data for transmission to a base station using a physical uplink shared channel (PUSCH) using a carrier above the 52.6 GHz carrier frequency.

15. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further configure the one or more processors to cause the UE to:

insert a guard interval (GI) sequence before and after the DM-RS sequence within a single carrier with frequency domain equalizer (SC-FDE) block, wherein the GI sequence is independently generated from the DM-RS sequence.

16. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further configure the one or more processors to cause the UE to:

insert a guard interval (GI) sequence before the DM-RS sequence within a single carrier with frequency domain equalizer (SC-FDE) block, wherein a length of the DM-RS sequence equals a Fast Fourier Transform (FFT) size and the GI sequence is a portion of the DM-RS sequence.

17. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further configure the one or more processors to cause the UE to:

apply a hopping pattern to the base sequence, wherein the hopping pattern is initialized using at least one of the following;

a slot index, a single carrier with frequency domain equalizer (SC-FDE) block index, a SC-FDE sub-block index, or a configurable ID.

18. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further configure the one or more processors to cause the UE to:

apply a block-wised orthogonal cover code (OCC) to the DM-RS sequence in time domain to generate a block-wised spread DM-RS sequence, the block-wised spread DM-RS sequence associated with one of the plurality of available DM-RS APs.

19. The non-transitory computer-readable storage medium of claim 18, the block-wised OCC is applied on a block level or a sub-block level.

20. The non-transitory computer-readable storage medium of claim 18, wherein the instructions further configure the one or more processors to cause the UE to:

decode downlink control information (DCI) indicating an AP for use during the uplink data transmission;

generate the block-wised spread DM-RS sequence based on the indicated AP; and

encode the block-wised spread DM-RS sequence with the uplink data for transmission to the base station using the PUSCH.