PHASE LOCKED LOOP CIRCUITS, CLOCK SIGNAL GENERATORS COMPRISING DIGITAL-TO-TIME CONVERT CIRCUITS, OPERATING METHODS THEREOF AND WIRELESS COMMUNICATION DEVICES
First Claim
1. A clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator comprising:
- a digital-to-time converter (DTC) configured todelay the reference clock signal based on an input code to generate a delay clock signal, andoutput the delay clock signal;
a DTC controller configured todetermine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, andgenerate the input code based on the initial gain value; and
a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.
1 Assignment
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Accused Products
Abstract
Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.
6 Citations
25 Claims
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1. A clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator comprising:
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a digital-to-time converter (DTC) configured to delay the reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal; a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value; and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A phase locked loop circuit comprises:
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a phase locked loop configured to generate a target output clock signal based on a division clock signal of a previously generated output clock signal and an input clock signal, the target output clock signal being locked to the input clock signal; a modulator configured to change a division ratio of the phase locked loop, and output an error value occurring according to the changed division ratio; a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate the input clock signal, and provide the input clock signal to the phase locked loop; and a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19-22. -22. (canceled)
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23. A wireless communication device comprises:
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a signal processor configured to process a transmission signal and a receiving signal in a base band, and output a frequency control signal; a transceiver configured to time-serially perform a transmission operation and a receiving operation; and a clock signal generator configured to generate an target output clock signal used to provide a frequency for sampling the transmission signal and the receiving signal in response to the frequency control signal, wherein the clock signal generator comprises; a phase locked loop configured to generate the target output clock signal based on a division clock signal of a previously generated output clock signal and an input clock signal the target output clock signal being locked to the input clock signal, and change a division ratio used to generate the division clock signal based on the frequency control signal, a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate the input clock signal, and provide the input clock signal to the phase locked loop; and a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of the previously generated output clock signal, and generate the input code based on the initial gain value. - View Dependent Claims (24)
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25. (canceled)
Specification