SCALABLE DATA ACCESS SYSTEM AND METHODS OF ELIMINATING CONTROLLER BOTTLENECKS

• US 20190310773A1
• Filed: 06/24/2019
• Published: 10/10/2019
• Est. Priority Date: 04/08/2016
• Status: Active Grant

• Current Assignee: Branislav Radovanovic
• Original Assignee: Vallteraus, LLC
• Inventors: Radovanovic, Branislav
• Granted Patent: US 10,949,093 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS
• CPC Class Codes: G06F 2212/286 Mirrored cache memory
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance. The nFE_SAN and FE_SAN controllers facilitate Converged I/O Interface by simultaneously supporting storage I/O and network traffic.

Claims

1. A method of writing write data to at least one storage device comprising:

generating a write request in a computer processor;

passing the write request to a front-end storage controller (nFE_SAN);

copying the write data to a first and a second cache memory of the nFE_SAN;

generating a write lock request and transmitting the write lock request from the nFE_SAN over a network interconnect selected from a first and a second storage area interconnect to a back-end storage controller (nBE_SAN);

returning a write lock grant from the nBE_SAN to the nFE_SAN;

upon completing copying the write data to the first and second cache memory of the nFE_SAN and receiving the write lock grant from the nBE_SAN, the nFE_SAN providing a write complete signal to the computer processor;

copying the write data over a network interconnect selected from the first and second storage area interconnect to the nBE_SAN; and

writing, by the BE_SAN, the write data to the at least one storage device.

2. The method of claim 1 wherein, upon failure of the first cache memory of the nFE_SAN, the write data is copied from the second cache memory of the nFE_SAN to the nBE_SAN.

3. A method of writing write data to at least one storage device comprising:

generating a write request in a computer processor;

passing the write request to a front-end storage controller (nFE_SAN);

copying the write data to a first and a second cache memory of the nFE_SAN;

generating a write lock request and transmitting the write lock request from the nFE_SAN over a network interconnect selected from a first and a second storage area interconnect to a selected back-end storage controller (nBE_SAN), the nBE_SAN selected from a first and a second nBE_SAN of a plurality of nBE_SANs according to logical block addresses (LBAs) identification associated with the write request, where a first of the nBE_SANs is assigned to write data associated with a first and second LBAs, and a second nBE_SAN is assigned to write data associated with third LBAs, the first, second, and third LBAs being different and the first nBE_SAN being different from the second nBE_SAN;

returning a write lock grant from the selected nBE_SAN to the nFE_SAN;

upon completing copying the write data to the first and second cache memory of the nFE_SAN and receiving the write lock grant from the selected nBE_SAN, the nFE_SAN providing a write complete signal to the computer processor;

copying the write data over a network interconnect selected from the first and second storage area interconnect to the selected nBE_SAN; and

writing, by the selected BE_SAN, the write data to the at least one storage device.

4. The method of claim 3 wherein, upon detecting overload of the first nBE_SAN by frequent accesses to the second LBAs, copying data associated with the second LBAs from the first nBE_SAN to the second nBE_SAN and directing further references to the second LBAs to the second nBE_SAN.