EXTENSIBLE STORAGE SYSTEM AND METHOD
First Claim
1. A data storage system comprising:
- a primary controller chip comprising a first host interface and a first extension interface, the first host interface configured to be coupled to a host device; and
a secondary controller chip coupled to the first extension interface,wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the first host interface is greater than a bandwidth of the first extension interface, the bandwidth of the first host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the first host interface, andwherein the primary controller chip is configured to;
receive a host data access command from the host device via the first host interface;
transfer the host data access command to the secondary controller chip; and
provide a notification that execution of the host data access command has been completed.
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Accused Products
Abstract
A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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Citations
20 Claims
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1. A data storage system comprising:
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a primary controller chip comprising a first host interface and a first extension interface, the first host interface configured to be coupled to a host device; and a secondary controller chip coupled to the first extension interface, wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the first host interface is greater than a bandwidth of the first extension interface, the bandwidth of the first host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip is configured to utilize less than an entirety of the bandwidth of the first host interface, and wherein the primary controller chip is configured to; receive a host data access command from the host device via the first host interface; transfer the host data access command to the secondary controller chip; and provide a notification that execution of the host data access command has been completed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A machine-implemented method, comprising:
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receiving a host data access command at a primary controller chip coupled to a host device via a host interface of the primary controller chip; transferring the host data access command from the primary controller chip to a secondary controller chip coupled to the primary controller chip via an extension interface of the primary controller chip, wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the host interface is greater than a bandwidth of the extension interface, the bandwidth of the host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip utilizes less than an entirety of the bandwidth of the host interface; and providing a notification that execution of the host data access command has been completed. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An apparatus, comprising:
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means for receiving a host data access command at a primary controller chip coupled to a host device via a host interface of the primary controller chip; means for transferring the host data access command from the primary controller chip to a secondary controller chip coupled to the primary controller chip via an extension interface of the primary controller chip, wherein the secondary controller chip is one of one or more secondary controller chips, a bandwidth of the host interface is greater than a bandwidth of the extension interface, the bandwidth of the host interface is split among the primary controller chip and the one or more secondary controller chips, and each of the primary controller chip and the secondary controller chip utilizes less than an entirety of the bandwidth of the host interface; and means for providing a notification that execution of the host data access command has been completed. - View Dependent Claims (19, 20)
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Specification