SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGUREABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM
First Claim
1. A computer system, comprising:
- a DRAM memory;
a processor having reconfigurable application logic with a number of processing elements, the processor operable to access data within the DRAM memory;
a data maintenance block coupled to the DRAM memory and operable to signal the DRAM memory of one of a reconfigure condition and a post-reconfigure condition of the number of processing elements; and
a reconfigure controller coupled to the data maintenance block and operable to initiate direct memory access read requests, store data from said read requests prior to a reconfiguration of the number of processing elements and write stored data from said read requests after the reconfiguration of the number of processing elements.
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Accused Products
Abstract
A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.
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Citations
4 Claims
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1. A computer system, comprising:
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a DRAM memory; a processor having reconfigurable application logic with a number of processing elements, the processor operable to access data within the DRAM memory; a data maintenance block coupled to the DRAM memory and operable to signal the DRAM memory of one of a reconfigure condition and a post-reconfigure condition of the number of processing elements; and a reconfigure controller coupled to the data maintenance block and operable to initiate direct memory access read requests, store data from said read requests prior to a reconfiguration of the number of processing elements and write stored data from said read requests after the reconfiguration of the number of processing elements. - View Dependent Claims (2, 3, 4)
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Specification