SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGUREABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM

• US 20190310785A1
• Filed: 06/24/2019
• Published: 10/10/2019
• Est. Priority Date: 05/27/2014
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Labs, LLC (Freeman Capital Partners LP)
• Inventors: Tewalt, Timothy J.
• Granted Patent: US 11,320,999 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting

Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Claims

1. A computer system, comprising:

a DRAM memory;

a processor having reconfigurable application logic with a number of processing elements, the processor operable to access data within the DRAM memory;

a data maintenance block coupled to the DRAM memory and operable to signal the DRAM memory of one of a reconfigure condition and a post-reconfigure condition of the number of processing elements; and

a reconfigure controller coupled to the data maintenance block and operable to initiate direct memory access read requests, store data from said read requests prior to a reconfiguration of the number of processing elements and write stored data from said read requests after the reconfiguration of the number of processing elements.

2. The computer system of claim 1 wherein said reconfigurable processor comprises an FPGA.

3. The computer system of claim 1 wherein the data maintenance block include a first block RAM and the reconfigure controller includes a second block RAM, the contents of the second block RAM being stored within the first block RAM during reconfiguration of the number of processing elements.

4. The computer system of claim 1, wherein the signal for the post-configuration condition includes a clock enable signal to the DRAM memory.