PIXELS AND REFERENCE CIRCUITS AND TIMING TECHNIQUES

• US 20190311676A1
• Filed: 06/25/2019
• Published: 10/10/2019
• Est. Priority Date: 07/24/2015
• Status: Active Application

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Azizi, Yaser
• Application Number:
  US16/451,216
• Publication Number:
  US 20190311676A1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

What is disclosed are systems and methods of compensation of images produced by active matrix light emitting diode device (AMOLED) and other emissive displays. Anomalies in luminance produced by pixel circuits and bias currents produced by current biasing circuits for driving current biased voltage programmed pixels are corrected through calibration and compensation while re-using existing data or other lines that can be controlled individually to perform said calibration and compensation.

Claims

1-16. -16. (canceled)

17. A display system comprising:

a plurality of pixels, each pixel including a light-emitting device,

a plurality of monitor lines, each monitor line coupled to a corresponding pixel at a first end of the monitor line;

a plurality of data lines, each data line coupled to a corresponding pixel at a first end of the data line;

a plurality of switch multiplexers, each switch multiplexer coupled to a second end of a data line and a second end of a monitor line, each switch multiplexer coupled to a signal line and comprising a plurality of switches for coupling the signal line to the data line or the monitor line.

18. The display system of claim 17, wherein each pixel is coupled to a group of said plurality of monitor lines, each monitor line of the group of monitor lines corresponding to each subpixel of the pixel, and wherein each pixel is coupled to a group of said plurality of data lines, each data line of the group of data lines corresponding to each subpixel of the pixel.

19. The display system of claim 17, wherein each switch multiplexer is coupled to a plurality of control lines for controlling the plurality of switches.

20. The display system of claim 19 further comprising:

a source driver circuit coupled to the signal lines.

21. The display system of claim 20 further comprising:

a monitoring circuit coupled to the signal lines.

22. The display system of claim 21 further comprising:

an address driver circuit coupled to the control lines.

23. The display system of claim 17, wherein the plurality of switches of each switch multiplexer comprises a first switch coupled between the signal line and the monitor line and comprises a second switch coupled between the signal line and the data line.

24. The display system of claim 23, wherein each first switch of each switch multiplexer is coupled to a first control line for controlling the first switch and wherein each second switch of each switch multiplexer is coupled to a second control line for controlling the second switch.

25. The display system of claim 17, further comprising a plurality of reference voltage lines, each reference voltage line coupled between a corresponding switch multiplexer and a reference voltage supply, said plurality of switches of each switch multiplexer for coupling the reference voltage supply to the monitor line coupled to the switch multiplexer.

26. The display system of claim 25, wherein each pixel is coupled to a group of said plurality of monitor lines, each monitor line of the group of monitor lines corresponding to a subpixel of the pixel, wherein each pixel is coupled to a group of said plurality of data lines, each data line of the group of data lines corresponding to a subpixel of the pixel, and wherein each monitor line of said group of said plurality of monitor lines is coupleable via a corresponding switch multiplexer to the reference voltage line coupled to the switch multiplexer.

27. The display system of claim 25, wherein each switch multiplexer is coupled to a plurality of control lines for controlling the plurality of switches.

28. The display system of claim 27 further comprising:

a source driver circuit coupled to the signal lines.

29. The display system of claim 28 further comprising:

a monitoring circuit coupled to the signal lines.

30. The display system of claim 29 further comprising:

an address driver circuit coupled to the control lines.

31. The display system of claim 25, wherein the plurality of switches of each switch multiplexer comprises a first switch coupled between the signal line and the monitor line, comprises a second switch coupled between the signal line and the data line, and comprises a third switch coupled between the monitor line and the reference voltage line.

32. The display system of claim 31, wherein each first switch of each switch multiplexer is coupled to a first control line for controlling the first switch, wherein each second switch of each switch multiplexer is coupled to a second control line for controlling the second switch, and wherein each third switch of each switch multiplexer is coupled to a third control line for controlling the third switch.