GOA CIRCUIT AND DRIVING METHOD THEREOF, AND TOUCH DISPLAY APPARATUS

• US 20190311690A1
• Filed: 04/03/2019
• Published: 10/10/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: CHEN, Shuai, DONG, Xing, TIAN, Zhenguo, LIANG, Xuebo, XIONG, Lijun, TANG, Xiuzhu, HU, Shuang
• Granted Patent: US 10,614,769 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A GOA circuit includes a plurality of GOA units. First input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, and a first input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located in front of the any one of other GOA units. Second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, and a second input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located behind the any one of other GOA units. N is the number of clock signals in one clock period. N/2 cascaded GOA units of the GOA circuit are included in a pull-up node potential holding unit, and output terminals of the N/2 cascaded GOA units are not coupled to gate lines.

Claims

1. A GOA circuit, comprising a plurality of cascaded GOA units, wherein each GOA unit includes a first input terminal, a second input terminal, an output terminal, voltage terminals and a clock signal terminal;

and the GOA circuit is configured to receive N clock signals in one clock period, the clock signal terminal of the GOA unit is configured to receive one of the N clock signals in one clock period, and N is a positive even number;

first input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, a first input terminal of a (N/2+1)th-level GOA unit is coupled to an output terminal of the first-level GOA unit, a first input terminal of a (N/2+2)th-level GOA unit is coupled to an output terminal of a second-level GOA unit, and so on;

second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, a second input terminal of a (N/2+1)th last-level GOA unit is coupled to an output terminal of the last-level GOA unit, a second input terminal of a (N/2+2)th last-level GOA unit is coupled to an output terminal of a second last-level GOA unit, and so on; and

N/2 cascaded GOA units of the plurality of cascaded GOA units are included in a pull-up node potential holding unit, and output terminals of the GOA units in the pull-up node potential holding unit are not coupled to gate lines.

2. The GOA circuit according to claim 1, wherein the GOA unit further includes a first input sub-circuit, a second input sub-circuit, an output sub-circuit, a pull-down control sub-circuit and a pull-down sub-circuit;

the first input sub-circuit is coupled to the first input terminal and a pull-up node, and the first input sub-circuit is configured to input a signal from the first input terminal to the pull-up node under control of the first input terminal;

the second input sub-circuit is coupled to the second input terminal, the pull-up node and a first voltage terminal, and the second input sub-circuit is configured to output a signal from the first voltage terminal to the pull-up node under control of the second input terminal;

the output sub-circuit is coupled to the pull-up node, the clock signal terminal and the output terminal, and the output sub-circuit is configured to output a signal from the clock signal terminal to the output terminal under control of a potential at the pull-up node;

the pull-down control sub-circuit is coupled to a second voltage terminal, the pull-up node, a pull-down node and the first voltage terminal, the pull-down control sub-circuit is configured to output the signal from the first voltage terminal to the pull-down node under control of a potential at the pull-up node, and output a voltage from the second voltage terminal to the pull-down node under control of the second voltage terminal; and

the pull-down sub-circuit is coupled to the pull-down node, the pull-up node, the output terminal and the first voltage terminal, and the pull-down sub-circuit is configured to output the signal from the first voltage terminal to the the output terminal and the pull-up node under control of a potential at the pull-down node.

3. The GOA circuit according to claim 2, wherein each of (N/2)-level GOA units disposed behind the pull-up node potential holding unit further includes a denoising sub-circuits, the denoising sub-circuit of any GOA unit of the (N/2)-level GOA units located behind the pull-up node potential holding unit is coupled to the first voltage terminal, an output terminal of the same-level GOA unit and an output terminal of a corresponding-level GOA unit in the pull-up node potential holding unit, and the denoising sub-circuit is configured to denoise an output signal of the output terminal of the same-level GOA unit under control of the output signal from the output terminal of the corresponding-level GOA unit in the pull-up node potential holding unit in a touch scan period.

4. The GOA circuit according to claim 2, wherein the first input sub-circuit includes a first transistor, a gate and a first electrode of the first transistor is coupled to the first input terminal, and a second electrode of the first transistor is coupled to the pull-up node.

5. The GOA circuit according to claim 2, wherein the second input sub-circuit includes a second transistor, a gate of the second transistor is coupled to the second input terminal, a first electrode of the second transistor is coupled to the pull-up node, and a second electrode of the second transistor is coupled to the first voltage terminal.

6. The GOA circuit according to claim 2, wherein the output sub-circuit includes a third transistor and a first capacitor;

a gate of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to the clock signal terminal, and a second electrode of the third transistor is coupled to the output terminal; and

one end of the first capacitor is coupled to the pull-up node, and another end of the first capacitor is coupled to the output terminal.

7. The GOA circuit according to claim 2, wherein the pull-down control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

a gate and a first electrode of the fourth transistor are coupled to the second voltage terminal, and a second electrode of the fourth transistor is coupled to a gate of the fifth transistor and a first electrode of the seventh transistor; and

a first electrode of the fifth transistor is coupled to the second voltage terminal, and a second electrode of the fifth transistor is coupled to the pull-down node; and

a gate of the sixth transistor is coupled to the pull-up node, a first electrode of the sixth transistor is coupled to the pull-down node, and a second electrode of the sixth transistor is coupled to the first voltage terminal; and

a gate of the seventh transistor is coupled to the pull-up node, and a second electrode of the seventh transistor is coupled to the first voltage terminal.

8. The GOA circuit according to claim 2, wherein the pull-down sub-circuit includes an eighth transistor and a ninth transistor;

a gate of the eighth transistor is coupled to the pull-down node, a first electrode of the eighth transistor is coupled to the pull-up node, and a second electrode of the eighth transistor is coupled to the first voltage terminal; and

a gate of the ninth transistor is coupled to the pull-down node, a first electrode of the ninth transistor is coupled to the output terminal, and a second electrode of the nine transistor is coupled to the first voltage terminal.

9. The GOA circuit according to claim 3, wherein the denoising sub-circuit includes a tenth transistor, a gate of the tenth transistor is coupled to the output terminal of the corresponding-level GOA unit in the pull-up node potential holding unit, a first electrode of the tenth transistor is coupled to the output terminal of the same-level GOA unit, and a second electrode of the tenth transistor is coupled to the first voltage terminal.

10. The GOA circuit according to claim 4, wherein the transistor is a N-type transistor or a P-type transistor.

11. A method of driving the GOA circuit according to claim 1, the method comprising:

in a touch scan period, providing low level clock signals to (N/2)-level GOA units located behind the pull-up node potential holding unit, so that gate line scan signals are not output from the (N/2)-level GOA units located behind the pull-up node potential holding unit in the touch scan period; and

in the touch scan period, providing a high level clock signal to each GOA unit in the pull-up node potential holding unit, so that a high level signal is output from an output terminal of each GOA unit in the pull-up node potential holding unit, thereby causing that pull-up nodes of the (N/2)-level GOA units located behind the pull-up node potential holding unit are maintained at a high level in the touch scan period.

12. The method of driving the GOA circuit according to claim 11, wherein each of the (N/2)-level GOA units located behind the pull-up node potential holding unit includes a denoising sub-circuit, and the method further includes:

in the touch scan period, controlling the denoising sub-circuit by using a high level signal output from an output terminal of a corresponding GOA unit in the pull-up node potential holding unit, so that the denoising sub-circuit denoises an output signal from a corresponding one of the (N/2)-level GOA units located behind the pull-up node potential holding unit.

13. The method of driving the GOA circuit according to claim 11, wherein the method further includes:

in an input period, inputting, by a first input sub-circuit, a signal from the first input terminal to a pull-up node under control of the first input terminal;

in an output period, outputting, by an output sub-circuit, a signal from the clock signal terminal as a gate line scan signal to the output terminal under control of a potential at the pull-up node; and

in a reset period, pulling down, by a second input sub-circuit, the potential at the pull-up node to a potential at a first voltage terminal under control of the second input terminal, outputting, by a pull-down control sub-circuit, a signal from a second voltage terminal to a pull-down node under control of the second voltage terminal, and pulling down, by a pull-down sub-circuit, potentials at the output terminal and the pull-up node to the potential at the first voltage terminal under control of a potential at the pull-down node, wherein

the input period, the output period and the reset period are included in a display period.

14. A touch display apparatus, comprising the GOA circuit according to claim 1.