RESISTIVE MEMORY DEVICE HAVING REDUCED CHIP SIZE AND OPERATION METHOD THEREOF
First Claim
1. A memory device comprising:
- a voltage generator generating a write word line voltage according to activation of a write enable signal;
a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage;
a word line power path arranged in common with respect to the write word line voltage and the read word line voltage and connected to the switch circuit to receive the output word line voltage; and
a word line driver driving a word line of the memory device by activating the word line by using the write word line voltage or the read line voltage according to a voltage applied to the word line power path,wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command.
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Abstract
A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
3 Citations
20 Claims
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1. A memory device comprising:
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a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage; a word line power path arranged in common with respect to the write word line voltage and the read word line voltage and connected to the switch circuit to receive the output word line voltage; and a word line driver driving a word line of the memory device by activating the word line by using the write word line voltage or the read line voltage according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 12)
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8. A memory device comprising:
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a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage; a word line power path connected to the switch circuit to receive the output word line voltage; and a word line driver driving a word line of the memory device according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable-signal in response to the received write command, wherein the voltage generator is a charge pump generating the write word line voltage by performing a charge pumping operation in response to the activation of the write enable signal.
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13. A memory device comprising:
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a voltage generator generating a write word line voltage according to activation of a write enable signal; a word line power path connected to a first node receiving the write word line voltage and a second node receiving read word line voltage in a switchable manner; a word line driver driving a word line of the memory device according to a voltage applied to the word line power path; and control logic receiving a write command and a read command together during an activation period of the write enable signal, performing a write operation corresponding to the write command within the activation period, and performing a read operation corresponding to the read command within the same activation period. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification