SEMICONDUCTOR DEVICE

• US 20190311766A1
• Filed: 09/10/2018
• Published: 10/10/2019
• Est. Priority Date: 04/05/2018
• Status: Abandoned Application

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: KUSHIDA, Keiichi
• Application Number:
  US16/126,529
• Publication Number:
  US 20190311766A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 20/363 Gate conductor programmed

Abstract

A semiconductor device includes a latch including a first-node and a second-node. A first-transistor is between the first-node and a first-BL and has a gate connected to a WL. A second-transistor is between the second-node and a second-BL and has a gate connected to the WL. A power-supply line is connected to the latch. A third-transistor is connected between the first-node and a reference-voltage source. A fourth-transistor is between the second-node and the reference-voltage source and has a gate connected to the reference-voltage source. A signal line is connected to a gate of the third-transistor. In a first-mode, the power-supply line supplies a first-voltage to the latch and the signal line brings the third-transistor to a non-conduction state. In a second-mode, the power-supply line supplies a second-voltage to the latch and the signal line brings the third-transistor to a conduction state and connects the first-node to the reference-voltage source.

Claims

1. A semiconductor device comprising:

a latch circuit including a first node and a second node being capable of retaining data of polarities opposite to each other, respectively;

a first transistor electrically connected between the first node and a first bit line and having a gate electrode electrically connected to a word line;

a second transistor electrically connected between the second node and a second bit line and having a gate electrode electrically connected to the word line;

a power-supply line electrically connected to the latch circuit;

a third transistor electrically connected between the first node and a reference voltage source;

a fourth transistor electrically connected between the second node and the reference voltage source and having a gate electrode electrically connected to the reference voltage source; and

a signal line electrically connected to a gate electrode of the third transistor, wherein

the power-supply line supplies a first voltage to the latch circuit and the signal line brings the third transistor to a non-conduction state in a first mode, and

the power-supply line supplies a second voltage to the latch circuit and the signal line brings the third transistor to a conduction state and electrically connects the first node to the reference voltage source in a second mode.

2. The device of claim 1, wherein

the latch circuit stores data in the first and second nodes in the first mode, and

the third transistor electrically connects the first node to the reference voltage source and the fourth transistor electrically disconnects the second node from the reference voltage source in the second mode.

3. The device of claim 1, wherein the first and second transistors transmit voltages of the first and second nodes to the first and second bit lines, respectively, in response to selection of the word line at a time of data read in the first and second modes.

4. The device of claim 1, wherein

the first and second transistors transmit voltages from the first and second bit lines to the first and second nodes, respectively, in response to selection of the word line at a time of data write in the first mode, and

data write is not performed in the second mode.

5. The device of claim 1, wherein

in the first mode, the latch circuit functions as an SRAM (Static Random Access Memory), and

in the second mode, the latch circuit and the third and fourth transistors function as a ROM (Read-Only Memory).

6. The device of claim 2, wherein

in the first mode, the latch circuit functions as an SRAM, and

in the second mode, the latch circuit and the third and fourth transistors function as a ROM.

7. The device of claim 3, wherein

in the first mode, the latch circuit functions as an SRAM, and

in the second mode, the latch circuit and the third and fourth transistors function as a ROM.

8. The device of claim 4, wherein

in the first mode, the latch circuit functions as an SRAM, and

in the second mode, the latch circuit and the third and fourth transistors function as a ROM.

9. The device of claim 1, wherein the power-supply line extends substantially in parallel to the word line.

10. The device of claim 2, wherein the power-supply line extends substantially in parallel to the word line.

11. The device of claim 1, wherein the signal line extends substantially in parallel to the word line.

12. The device of claim 2, wherein the signal line extends substantially in parallel to the word line.

13. The device of claim 1, wherein

assuming the latch circuit and the first to fourth transistors as one unit,

a plurality of the units are provided to correspond to the word line and the first and second bit lines,

the units are connected in common to the word line,

the power-supply line is connected in common to the latch circuits of the units, and

the signal line is selectively connected to gate electrodes of either the third transistors or the fourth transistors in the units.

14. The device of claim 2, wherein

assuming the latch circuit and the first to fourth transistors as one unit,

a plurality of the units are provided to correspond to the word line and the first and second bit lines,

the units are connected in common to the word line,

the power-supply line is connected in common to the latch circuits of the units, and

the signal line is selectively connected to gate electrodes of either the third transistors or the fourth transistors in the units.

15. The device of claim 13, wherein

ones of the units having the third transistors connected to the signal line output data of a first logic in the second mode, and

ones of the units having the fourth transistors connected to the signal line output data of a second logic opposite to the first logic in the second mode.

16. The device of claim 14, wherein

ones of the units having the third transistors connected to the signal line output data of a first logic in the second mode, and

ones of the units having the fourth transistors connected to the signal line output data of a second logic opposite to the first logic in the second mode.

17. A semiconductor device comprising:

a latch circuit including a first node and a second node being capable of retaining data of polarities opposite to each other, respectively;

a power-supply line electrically connected to the latch circuit;

a ROM circuit electrically connected between the first node and a reference voltage source and between the second node and the reference voltage source; and

a signal line electrically connected to the ROM circuit, wherein

the power-supply line supplies a first voltage to the latch circuit to enable the latch circuit to retain data, and the signal line supplies a third voltage to the ROM circuit to enable the ROM circuit to electrically disconnect the first and second nodes from the reference voltage source in a first mode, and

the power-supply line supplies a second voltage to the latch circuit to cause the latch circuit not to retain data, and the signal line supplies a fourth voltage to the ROM circuit to enable the ROM circuit to electrically connect either the first node or the second node to the reference voltage source in a second mode.