NON-VOLATILE STORAGE SYSTEM WITH ADJUSTABLE SELECT GATES AS A FUNCTION OF TEMPERATURE

• US 20190311770A1
• Filed: 04/04/2018
• Published: 10/10/2019
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Gupta, Mahim Raj, Purahmad, Mohsen, Lei, Bo, Lai, Joanna, Costa, Xiying
• Granted Patent: US 10,573,388 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.

Claims

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells arranged in groups of memory cells, each group of memory cells comprising data memory cells and one or more select gates, the select gates are programmable; and

one or more control circuits in communication with the plurality of non-volatile memory cells, the one or more control circuits configured to program a select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming the select gate identified to be programmed if the temperature at the non-volatile memory cells is not greater than the minimum temperature.

2. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to defer programming the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature.

3. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured identify one or more select gates to be programmed by testing whether threshold voltages of the one or more select gates are within an acceptable range of threshold voltages.

4. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to program the select gate identified to be programmed by first lowering a threshold voltage for the select gate and subsequently raising the threshold voltage for the select gate.

5. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to program the select gate identified to be programmed by first performing erasing of the select gate and subsequently programming the select gate.

6. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to program the select gate identified to be programmed by adjusting a non-volatile property of the select gate.

7. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not greater than the minimum temperature, the one or more control circuits configured to program the select gate identified to be programmed after performing the dummy memory operations on the plurality of non-volatile memory cells.

8. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits configured to perform multiple read operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not greater than the minimum temperature, the multiple read operations are not performed in response to a request to read from a host in communication with the non-volatile storage apparatus, the one or more control circuits configured to program the select gate identified to be programmed after performing the read operations on the plurality of non-volatile memory cells.

9. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells comprise vertical NAND strings with charge trapping regions, the vertical NAND strings include multiple drain side select gates per vertical NAND string and source side select gates, the select gate identified to be programmed is one of the drain side select gates.

10. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are positioned on a memory die; and

the one or more control circuits comprise a controller off of and connected to the memory die, the controller configured to request the temperature at the non-volatile memory cells from the memory die.

12. The non-volatile storage apparatus of claim 1, wherein the one or more control circuits are configured to:

test and determine that drain side select gates of a first block need to be programmed;

determine if a current temperature is high enough;

program the drain side select gates of the first block using high temperature parameters if the current temperature is high enough;

add the first block to a queue if the current temperature is not high enough and the queue is not full,

program drain side select gates for blocks in the queue using high temperature parameters during idle time for the one or more control circuit when the temperature is high enough,

perform dummy memory operations for the first block if the temperature is not high enough and the queue is full, and

after performing the dummy operations, program drain side select gates for the first block using high temperature parameters if the temperature is high enough and program drain side select gates for the first block using low temperature parameters if the temperature is not high enough.

11. The non-volatile storage apparatus of claim 11, wherein:

the one or more control circuits configured to add to a data structure one or more indications of select gates identified to be programmed if the temperature is not greater than the minimum temperature, the one or more control circuits configured to program select gates indicated in the data structure during a future idle time when the temperature is greater than the minimum temperature.

13. A non-volatile memory system, comprising:

a memory die, the memory die includes a plurality of non-volatile storage elements arranged in groups of connected non-volatile storage elements, each group of connected non-volatile storage elements comprising one or more select gates, the select gates have programmable threshold voltages; and

a controller connected to the memory die, the controller configured to identify select gates to be programmed, the controller configured to request temperature from the memory die, the controller configured to presently program select gates identified to be programmed if the temperature is high enough, the controller configured to add to a data structure one or more indications of select gates identified to be programmed if the temperature is not high enough, the controller configured to program select gates indicated in the data structure during a future idle time when the temperature is high enough.

14. A non-volatile memory system, according to claim 13, wherein:

the controller is configured to perform dummy memory operations on the memory die to warm the memory die if the temperature is not high enough and program select gates identified to be programmed after performing the dummy memory operations on the memory die.

15. A non-volatile memory system, according to claim 13, wherein:

the memory die includes a temperature sensor, the memory die uses the temperature sensor to sense current temperature and report the current temperature in response to the request for temperature from the controller.

16-20. -20. (canceled)