SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE

• US 20190311774A1
• Filed: 11/08/2018
• Published: 10/10/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Seong Ju
• Granted Patent: US 10,818,372 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49 wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.

Claims

1. A semiconductor system comprising:

a first semiconductor device configured to control a test mode, configured to output a chip identification, and configured to receive external data; and

a second semiconductor device configured to include a plurality of memory chips,

wherein, while a write operation is performed in the test mode, one or more memory chips from the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated, and

wherein at least two of the plurality of memory chips are activated in response to the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.

2. The semiconductor system of claim 1, wherein the external data outputted from the second semiconductor device during the read operation include information on whether the plurality of memory chips normally operate.

3. The semiconductor system of claim 1,

wherein the test mode includes a first test mode, a second test mode, and a third test mode;

wherein the plurality of memory chips include a first group of memory chips stacked on the first semiconductor device and a second group of memory chips stacked on the first group of memory chips;

wherein the read operation for two memory chips immediately adjacent to each other among the first group of memory chips or among the second group of memory chips is performed in the first test mode;

wherein the read operation for two memory chips separated from each other by at least one memory chip among the first group of memory chips or among the second group of memory chips is performed in the second test mode; and

wherein the read operation for any one among the first group of memory chips and for any one among the second group of memory chips is performed in the third test mode.

4. The semiconductor system of claim 3,

wherein the external data include first external data and second external data;

and

wherein one of the two memory chips performing the read operation in the first or second test mode outputs the input data stored therein as the first external data, and the other of the two memory chips performing the read operation in the first or second test mode outputs the input data stored therein as the second external data.

5. The semiconductor system of claim 3,

wherein the external data include first external data and second external data;

and

wherein one of the first group of memory chips, which performs the read operation in the third test mode, outputs the input data stored therein as the first external data; and

wherein one of the second group of memory chips, which performs the read operation in the third test mode, outputs the input data stored therein as the second external data.

6. The semiconductor system of claim 1,

wherein the external data include first external data and second external data;

wherein the plurality of memory chips include a first group of memory chips and a second group of memory chips;

wherein the first group of memory chips include first and second memory chips, each of the first and second memory chips stores the input data during the write operation, and the input data stored in any one selected from the first and second memory chips according to a logic level combination of the chip identification is outputted as the first external data based on a test control signal during the read operation; and

wherein the second group of memory chips include third and fourth memory chips, each of the third and fourth memory chips stores the input data during the write operation, and the input data stored in any one selected from the third and fourth memory chips according to a logic level combination of the chip identification is outputted as the second external data based on the test control signal during the read operation.

7. The semiconductor system of claim 6,

wherein the first and second memory chips are connected through a first sub-pad;

wherein the third and fourth memory chips are connected through a second sub-pad; and

wherein the first memory chip and the third memory chip are connected through a main pad.

8. The semiconductor system of claim 6, wherein the first to fourth memory chips are sequentially stacked.

9. A semiconductor device comprising:

a first group of memory chips vertically stacked, wherein one or more memory chips of the first group are activated during a write operation in a test mode to store input data into each of the memory chips that have been activated in the first group, and the input data stored in one or more of the memory chips of the first group, which is activated by a chip identification, is outputted as first external data through a first main pad during a read operation; and

a second group of memory chips vertically stacked, wherein one or more memory chips of the second group are activated during the write operation in the test mode to store the input data into each of the memory chips that have been activated in the second group, and the input data stored in one or more of the memory chips of the second group, which is activated by the chip identification, is outputted as second external data through a second main pad during the read operation.

10. The semiconductor device of claim 9, wherein the first group of memory chips include:

a first memory chip configured to store the input data during the write operation and configured to transmit the stored input data to a first sub-pad and to output the input data loaded on the first sub-pad as the first external data through the first main pad based on the chip identification during the read operation; and

a second memory chip configured to store the input data during the write operation and configured to output the stored input data through a second sub-pad based on the chip identification during the read operation.

11. The semiconductor device of claim 10, wherein the second group of memory chips include:

a third memory chip configured to store the input data during the write operation and configured to transmit the stored input data to a third sub-pad and to output the input data loaded on the third sub-pad as the second external data through the second main pad based on the chip identification during the read operation; and

a fourth memory chip configured to store the input data during the write operation and configured to output the stored input data through a fourth sub-pad based on the chip identification during the read operation.

12. The semiconductor device of claim 11,

wherein the first sub-pad and the second sub-pad are electrically connected to each other;

and

wherein the third sub-pad and the fourth sub-pad are electrically connected to each other.

13. The semiconductor device of claim 11,

wherein the first external data loaded on the first main pad are generated from the input data outputted from the first memory chip or the third memory chip;

and

wherein the second external data loaded on the second main pad are generated from the input data outputted from the second memory chip or the fourth memory chip.

14. The semiconductor device of claim 11,

wherein the test mode includes a first test mode and a second test mode;

wherein the read operation for two memory chips immediately adjacent to each other among the first to fourth memory chips is performed in the first test mode; and

wherein the read operation for two memory chips separated from each other by at least one memory chips among the first to fourth memory chips is performed in the second test mode.

15. The semiconductor device of claim 10, wherein the first memory chip includes:

a first identification creation circuit configured to change the chip identification based on a test control signal and a test mode signal to generate a first internal identification and a first set identification;

a first output control circuit configured to generate a first sub-control signal and a first main control signal based on the first set identification;

a first memory circuit configured to store the input data based on the chip identification or the first internal identification during the write operation and configured to output the stored input data as first internal data based on the chip identification or the first internal identification during the read operation;

a first data process circuit configured to output the first internal data as first transmission data; and

a first data output circuit configured to generate first output data from the first transmission data based on the first sub-control signal and configured to generate the first external data from the first output data based on the first main control signal.

16. The semiconductor device of claim 15, wherein the first data output circuit outputs the first output data loaded on the first sub-pad or second output data outputted from a second data output circuit as the first external data in the test mode.

17. The semiconductor device of claim 10, wherein the second memory chip includes:

a second identification creation circuit configured to change the chip identification based on a test control signal and a test mode signal to generate a second internal identification and a second set identification;

a second output control circuit configured to generate a second sub-control signal and a second main control signal based on the second set identification;

a second memory circuit configured to store the input data based on the chip identification or the second internal identification during the write operation and configured to output the stored input data as second internal data based on the chip identification or the second internal identification during the read operation;

a second data process circuit configured to output the second internal data as second transmission data; and

a second data output circuit configured to generate second output data from the second transmission data based on the second sub-control signal and configured to output the second output data to the first sub-pad through the second sub-pad.

18. The semiconductor device of claim 11, wherein the third memory chip includes:

a third identification creation circuit configured to change the chip identification based on a test control signal and a test mode signal to generate a third internal identification and a third set identification;

a third output control circuit configured to generate a third sub-control signal and a third main control signal based on the third set identification;

a third memory circuit configured to store the input data based on the chip identification or the third internal identification during the write operation and configured to output the stored input data as third internal data based on the chip identification or the third internal identification during the read operation;

a third data process circuit configured to output the third internal data as third transmission data; and

a third data output circuit configured to generate third output data from the third transmission data based on the third sub-control signal and configured to generate the second external data from the third output data based on the third main control signal.

19. The semiconductor device of claim 18, wherein the third data output circuit outputs the third output data loaded on the second sub-pad or fourth output data outputted from a fourth data output circuit as the second external data in the test mode.

20. The semiconductor device of claim 11, wherein the fourth memory chip includes:

a fourth identification creation circuit configured to change the chip identification based on a test control signal and a test mode signal to generate a fourth internal identification and a fourth set identification;

a fourth output control circuit configured to generate a fourth sub-control signal and a fourth main control signal based on the fourth set identification;

a fourth memory circuit configured to store the input data based on the chip identification or the fourth internal identification during the write operation and configured to output the stored input data as fourth internal data based on the chip identification or the fourth internal identification during the read operation;

a fourth data process circuit configured to output the fourth internal data as fourth transmission data; and

a fourth data output circuit configured to generate fourth output data from the fourth transmission data based on the fourth sub-control signal and configured to output the fourth output data to the second sub-pad through the fourth sub-pad.