SEMICONDUCTOR-PRODUCT TESTING DEVICE, METHOD FOR TESTING SEMICONDUCTOR PRODUCT, AND SEMICONDUCTOR PRODUCT

• US 20190311776A1
• Filed: 03/22/2019
• Published: 10/10/2019
• Est. Priority Date: 04/09/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: YAMADA, Naoki, MATSUMOTO, Yoshiyuki, NISHIMURA, Kazuhiro
• Granted Patent: US 10,886,001 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product includes a pattern memory that stores a part of the test pattern. The pattern memory is rewritten during a time when the semiconductor product is tested by a part of the test pattern stored in the pattern memory included in the semiconductor-product testing device.

Claims

1. A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product, the device comprising:

a pattern memory that stores a part of the test pattern,

wherein the pattern memory is rewritten during a time when the semiconductor product is tested by using the part of the test pattern stored in the pattern memory as a partial test pattern.

2. The semiconductor-product testing device according to claim 1,

wherein the pattern memory includes a first address region and a second address region that is different from the first address region,

the test pattern includes a plurality of test pattern portions, and

during a time when a first test pattern portion stored in the first address region is supplied to the semiconductor product as the partial test pattern and the semiconductor product is tested, a second test pattern portion that is different from the first test pattern portion is written in the second address region, thereby rewriting the pattern memory.

3. The semiconductor-product testing device according to claim 2,

wherein after testing the semiconductor product by the first test pattern portion stored in the first address region finishes, a third test pattern portion is written in the first address region.

4. The semiconductor-product testing device according to claim 3,

wherein the pattern memory includes a third address region that is different from the first address region and the second address region,

a fourth test pattern portion supplied to the semiconductor product next to the first test pattern portion is stored in the third address region, and

during a time when the fourth test pattern portion stored in the third address region is supplied to the semiconductor product and the semiconductor product is tested, the third test pattern portion is written in the first address region.

5. The semiconductor-product testing device according to claim 3,

wherein the first test pattern portion and the second test pattern portion each include a pattern data portion supplied to the semiconductor product and an expected pattern data portion, and

the semiconductor-product testing device further comprises:

a comparing unit that outputs a pattern comparison data portion based on output data outputted from the semiconductor product in response to the pattern data portion and the expected pattern data portion; and

a fail memory that is rewritten with the pattern comparison data portion outputted from the comparing unit.

6. The semiconductor-product testing device according to claim 5,

wherein the fail memory includes a first address region and a second address region which are different from each other, and

during a time when the pattern comparison data portion stored in the first address region of the fail memory is outputted, the pattern comparison data portion outputted from the comparing unit is written in the second address region of the fail memory.

7. The semiconductor-product testing device according to claim 6,

wherein the first test pattern portion and the second test pattern portion are supplied to the semiconductor-product testing device from a server connected to the semiconductor-product testing device, and

the pattern comparison data portion outputted from the fail memory is sequentially supplied to the server.

8. The semiconductor-product testing device according to claim 7,

wherein the semiconductor-product testing device and the server are wirelessly connected.

9. A method for testing a semiconductor product, comprising:

a test pattern portion storing step of dividing a test pattern for testing a semiconductor product into a plurality of test pattern portions and storing the test pattern portions in a pattern memory; and

a test pattern portion supplying of supplying the test pattern portions stored in the pattern memory to the semiconductor product,

wherein in the test pattern portion supplying step, during a time when a first test pattern portion stored in the pattern memory is supplied to the semiconductor product, the pattern memory is rewritten with a second test pattern portion supplied later than the first test pattern portion.

10. The method for testing a semiconductor product according to claim 9,

wherein the pattern memory includes a first address region and a second address region that is different from the first address region, and

in the test pattern portion supplying step, during a time when a test pattern portion stored in the first address region is supplied to the semiconductor product as the first test pattern portion, the second test pattern portion is written in the second address region, and

when supplying of the first test pattern portion to the semiconductor product finishes, a third test pattern portion that is different from the first test pattern portion and the second test pattern portion is written in the first address region.

11. The method for testing a semiconductor product according to claim 10,

wherein the first test pattern portion, the third test pattern portion, and the second test pattern portion include a pattern data portion supplied to the semiconductor product and an expected pattern data portion, and

the method further comprises:

a pattern comparison data outputting step of outputting a pattern comparison data portion based on output data outputted from the semiconductor product in response to the pattern data portion and the expected pattern data portion.

12. The method for testing a semiconductor product according to claim 11,

wherein the pattern comparison data outputting step includes a fail memory rewriting step of rewriting a fail memory with the pattern comparison data portion, and

in the fail memory rewriting step, the pattern comparison data portion is written in the fail memory during a time when the pattern comparison data portion stored in the fail memory is outputted.

13. The method for testing a semiconductor product according to claim 12,

wherein the fail memory includes a first address region and a second address region that is different from the first address region, and

during a time when the pattern comparison data portion stored in the first address region is outputted, the pattern comparison data portion is written in the second address region.

14. The method for testing a semiconductor product according to claim 13,

wherein the division of the test pattern is performed in a server, and

the pattern comparison data portion outputted in the pattern comparison data outputting step is supplied to the server.

15. The method for testing a semiconductor product according to claim 14,

wherein the plurality of test pattern portions are supplied wirelessly to a testing device including the pattern memory and the fail memory, and

the pattern comparison data portion outputted in the pattern comparison data outputting step is supplied wirelessly from the testing device to the server.

16. A semiconductor product that is tested by the method for testing a semiconductor product according to claim 9.