BONDING SURFACES FOR MICROELECTRONICS

• US 20190311911A1
• Filed: 04/01/2019
• Published: 10/10/2019
• Est. Priority Date: 04/05/2018
• Status: Active Grant

• Current Assignee: Invensas Bonding Technologies, Inc. (Adeia Inc.)
• Original Assignee: Invensas Bonding Technologies, Inc. (Adeia Inc.)
• Inventors: THEIL, Jeremy Alfred
• Granted Patent: US 11,056,348 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 2224/03005 for aligning the bonding area, e.g. marks, spacers
• CPC Class Codes: H01L 2224/03845 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/8001 Cleaning the bonding area, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/80031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/80047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/80345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/80359 Material
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/83031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/83896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/05442 SiO2

Abstract

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

Claims

1. A method for preparing a surface for direct-bonding during a microelectronics fabrication process, comprising:

overfilling cavities and trenches in a dielectric surface with a temporary filler having approximately equal chemical and mechanical responses to a chemical-mechanical planarization (CMP) process as the chemical and mechanical responses of the dielectric surface;

applying the CMP process to the temporary filler to planarize the temporary filler down to the dielectric surface; and

applying an etchant to the temporary filler to remove the temporary filler, the etchant selective to the temporary filler and nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches.

2. The method of claim 1, wherein the dielectric surface comprises a silicon oxide and the temporary filler comprises silicon nitride.

3. The method of claim 2, wherein the etchant comprises a phosphoric acid etchant to selectively remove the silicon nitride while being nonreactive with the silicon oxide surface.

4. The method of claim 1, further comprising direct-bonding the dielectric surface to another dielectric surface.

5. A method, comprising:

preparing a dielectric surface of a wafer or die for direct-bonding during a microelectronics fabrication process;

masking the dielectric surface with a resist material for etching a cavity in the dielectric surface;

etching the cavity in the dielectric surface with a first etchant;

stripping the resist material from the dielectric surface;

overflowing the cavity with a temporary filler to preserve edges of the cavity during a chemical-mechanical planarization (CMP) process, wherein the temporary filler possesses chemical and physical properties similar to the dielectric surface with respect to the chemical-mechanical planarization (CMP) process, and wherein the CMP process has approximately equal selectivity for the dielectric surface and the temporary filler;

applying the CMP process to planarize the temporary filler down to an interface between the temporary filler and the dielectric surface; and

removing the temporary filler with a second etchant selective to the temporary filler and nonreactive to the dielectric surface and nonreactive to inner surfaces of the cavity.

6. The method of claim 5, wherein the dielectric surface comprises a silicon oxide and the temporary filler comprises silicon nitride.

7. The method of claim 6, wherein the second etchant comprises a phosphoric acid to selectively etch the silicon nitride while remaining nonreactive to the silicon oxide surface.

8. The method of claim 6, wherein the cavity has a depth penetrating through a layer of the silicon oxide surface into an underlying layer below the layer of silicon oxide.

9. The method of claim 5, wherein preparing the dielectric surface before masking further comprises planarizing the dielectric surface to flatness comprising a depth of field of a photolithography system.

10. A bonded wafer, comprising:

a first horizontal bonding surface of the bonded wafer comprising a dielectric material, the first horizontal bonding surface flattened by a chemical-mechanical planarization (CMP) process;

a cavity in the first horizontal bonding surface;

a vertical wall of the cavity disposed at a 90°

angle to the first horizontal bonding surface;

wherein the dielectric material of the vertical wall of the cavity and the dielectric material of the first horizontal bonding surface comprise a 90°

corner at a line or a point, the corner comprised of the dielectric material defining an intersection of a vertical plane of the vertical wall of the cavity and a horizontal plane of the first horizontal bonding surface.

11. The bonded wafer of claim 10, wherein the first horizontal bonding surface is flattened by the chemical-mechanical planarization (CMP) process to a depth of field of a standard photolithography system.

12. The bonded wafer of claim 10, further comprising a second horizontal bonding surface direct-bonded to the first horizontal bonding surface.

13. The bonded wafer of claim 12, wherein the first horizontal bonding surface and the second horizontal bonding surface are direct-bonded together with an oxide-to-oxide direct bond.

14. The bonded wafer of claim 13, wherein the oxide-to-oxide direct bond between the first horizontal bonding surface and the second horizontal bonding surface is present at a geometric point where the vertical wall of the cavity and the horizontal bonding surface meet at the 90°

corner.

15. The bonded wafer of claim 12, wherein the dielectric material defining an intersection of a vertical plane of the vertical wall of the cavity and a horizontal plane of the first horizontal bonding surface comprises a square corner with no rounding to within a few angstroms.

16. The bonded wafer of claim 12, wherein the bonded wafer comprises two wafers direct-bonded together by a wafer-to-wafer process or comprises a die and a wafer direct-bonded together by a die-to-wafer process.