METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MOUNTING DEVICE

• US 20190311964A1
• Filed: 09/29/2017
• Published: 10/10/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Shinkawa Ltd. (Yamaha Corporation)
• Original Assignee: Shinkawa Ltd. (Yamaha Corporation)
• Inventors: NAKAMURA, Tomonori, MAEDA, Toru
• Granted Patent: US 10,847,434 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8109 Vacuum
• CPC Class Codes: H01L 2224/81092 Atmospheric pressure
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81907 Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/8309 Vacuum
• CPC Class Codes: H01L 2224/83092 Atmospheric pressure
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2224/83907 : Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 2224/9205 : Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/065 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/07 : the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/115 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.

Claims

1. A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method comprising:

a first lamination step of sequentially laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body;

a first permanent bonding step of heating and pressurizing the first chip laminate body from an upper side to thereby permanently bond collectively the one or more semiconductor chips;

a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on permanently bonded semiconductor chips to thereby form a second chip laminate body; and

a second permanent bonding step of heating and pressurizing the second chip laminate body from an upper side to thereby permanently bond collectively the two or more semiconductor chips.

2. The method of manufacturing a semiconductor device according to claim 1, wherein after the first lamination step and the first permanent bonding step are performed, the second lamination step and the second permanent bonding step are repeated until a total lamination number of the semiconductor chips reaches the target lamination number.

3. The method of manufacturing a semiconductor device according to claim 1, wherein

a plurality of disposition regions are set on the substrate,

in the first lamination step and the first permanent bonding step, one semiconductor chip is temporarily bonded and permanently bonded, and

the second lamination step is performed after the first permanent bonding step is performed in all of the two or more disposition regions.

6. The method of manufacturing a semiconductor device according to claim 2, wherein

a plurality of disposition regions are set on the substrate,

in the first lamination step and the first permanent bonding step, one semiconductor chip is temporarily bonded and permanently bonded, and

the second lamination step is performed after the first permanent bonding step is performed in all of the two or more disposition regions.

4. A mounting apparatus for laminating and mounting a prescribed target lamination number of semiconductor chips on a substrate, the mounting apparatus comprising:

a temporary bonding means for heating the semiconductor chips that is disposed on one of the substrate and a semiconductor chip in a lower layer, from an upper side at a first temperature and pressurizing with a first load to thereby temporarily bond thereof;

a permanent bonding means for heating a laminate body of one or more semiconductor chips, from an upper side of a chip laminate body at a second temperature greater than the first temperature and pressurizing with a second load to thereby permanently bond collectively the one or more semiconductor chips that form the laminate body; and

a control part for controlling the temporary bonding means and the permanent bonding means,

wherein the control part makes the temporary bonding means and the permanent bonding means perform;

a first lamination process for temporarily bonding sequentially one or more semiconductor chips on the substrate by the temporary bonding means to thereby form a first chip laminate body;

a first permanent bonding process for permanently bonding collectively the one or more semiconductor chips that form the first chip laminate body by the permanent bonding means;

a second lamination process for sequentially laminating while temporarily bonding two or more semiconductor chips on permanently bonded semiconductor chips by the temporary bonding means to thereby form a second chip laminate body; and

a second permanent bonding process for permanently bonding collectively the two or more semiconductor chips that form the second chip laminate body by the permanent bonding means.

5. A mounting apparatus for laminating and mounting a prescribed target lamination number of semiconductor chips on a substrate, the mounting apparatus comprising:

a bonding part for heating the semiconductor chips that is disposed on one of the substrate and a semiconductor chip in a lower layer, from an upper side at a first temperature and pressurizing with a first load to thereby temporarily bond thereof and for heating a laminate body of one or more semiconductor chips, from an upper side of a chip laminate body at a second temperature greater than the first temperature and pressurizing with a second load, to thereby permanently bond collectively the one or more semiconductor chips that form the laminate body; and

a control part for controlling the bonding part,

wherein the control part comprises;

a first lamination process part for sequentially temporarily bonding one or more semiconductor chips on the substrate by the bonding part to thereby form a first chip laminate body;

a first permanent bonding process part for collectively permanently bonding the one or more semiconductor chips which form the first chip laminate body by the bonding part;

a second lamination process part for sequentially laminating while temporarily bonding two or more semiconductor chips on permanently bonded semiconductor chips by the bonding part to thereby form a second chip laminate body; and

a second permanent bonding process part for collectively permanently bonding the two or more semiconductor chips which form the second chip laminate body by the bonding part.