Semiconductor Device and Method for Forming a Semiconductor Device

• US 20190311966A1
• Filed: 04/09/2019
• Published: 10/10/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Konrath, Jens Peter, Bergner, Wolfgang, Esteve, Romain, Gaisberger, Richard, Grasse, Florian, Hilsenbeck, Jochen, Joshi, Ravi Keshav, Kramp, Stefan, Krivec, Stefan, Lupina, Grzegorz, Narahashi, Hiroshi, Voerckel, Andreas, Woehlert, Stefan
• Granted Patent: US 11,217,500 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

Claims

1. A semiconductor device, comprising:

a contact metallization layer arranged on a semiconductor substrate;

an inorganic passivation structure arranged on the semiconductor substrate; and

an organic passivation layer,

wherein a first part of the organic passivation layer is located laterally between the contact metallization layer and the inorganic passivation structure,

wherein a second part of the organic passivation layer is located on top of the inorganic passivation structure,

wherein the first part of the organic passivation layer is located vertically closer to the semiconductor substrate than the second part of the organic passivation layer,

wherein a third part of the organic passivation layer is located on top of the contact metallization layer.

2. The semiconductor device of claim 1, wherein a thickness of the inorganic passivation structure is at least 500 nm.

3. The semiconductor device of claim 1, wherein the inorganic passivation structure comprises at least a silicon oxide layer having a thickness of at least 300 nm and at most 5 μ

m.

4. The semiconductor device of claim 1, wherein the inorganic passivation structure comprises at least a nitride layer having a thickness of at least 300 nm and at most 900 nm.

5. The semiconductor device of claim 1, wherein a lateral distance between the inorganic passivation structure and the contact metallization layer is larger than a thickness of the contact metallization layer.

6. The semiconductor device of claim 1, wherein a lateral distance between the inorganic passivation structure and the contact metallization layer is less than a width of the inorganic passivation structure.

7. The semiconductor device of claim 1, wherein a lateral distance between the inorganic passivation structure and an edge of the semiconductor substrate is at least 10 μ

m.

8. The semiconductor device of claim 1, wherein a thickness and/or a material of the inorganic passivation structure is configured such that an electric field at a surface of the inorganic passivation structure is at least 500 kV/cm in a blocking state of an electrical structure formed at the semiconductor substrate.

9. The semiconductor device of claim 1, wherein the organic passivation layer is a polyimide layer having a thickness of at least 1 μ

m and at most 50 μ

m.

10. The semiconductor device of claim 1, wherein a thickness and/or a material of the organic passivation structure is configured such that an electric field at a surface of the organic passivation layer is at most 500 kV/cm in a blocking state of an electrical structure formed at the semiconductor substrate.

11. The semiconductor device of claim 1, further comprising:

a barrier layer,

wherein a first part of the barrier layer is arranged between the contact metallization layer and the semiconductor substrate,

wherein a second part of the barrier layer is arranged between the inorganic passivation structure and the semiconductor substrate,

wherein the barrier layer extends at least from the first part of the barrier layer to the second part of the barrier layer.

12. The semiconductor device of claim 11, wherein the barrier layer comprises a first sublayer and a second sublayer, wherein the first sublayer comprises titanium, and wherein the second sublayer comprises a titanium aluminum alloy.

13. The semiconductor device of claim 11, wherein the first part of the barrier layer is arranged vertically between an intermediate oxide layer and the contact metallization layer, and wherein the second part of the barrier layer is arranged vertically between the inorganic passivation structure and the intermediate oxide layer.

14. The semiconductor device of claim 1, further comprising:

an adhesion layer,

wherein a first part of the adhesion layer is arranged between the contact metallization layer and the organic passivation layer,

wherein a second part of the adhesion layer is arranged between the inorganic passivation structure and the organic passivation layer,

wherein the adhesion layer extends at least from the first part of the adhesion layer to the second part of the adhesion layer.

15. The semiconductor device of claim 14, wherein the adhesion layer has a thickness of at most 100 nm and at least 10 nm.

16. The semiconductor device of claim 1, further comprising:

a mold compound structure in contact with the organic passivation layer.

17. The semiconductor device of claim 1, wherein the semiconductor substrate comprises:

a drift region of an electrical structure comprising dopants of a first conductivity type; and

an edge termination region comprising dopants of a second conductivity type,

wherein the edge termination region extends laterally from a contact region towards an edge of the semiconductor substrate at least partially beneath the inorganic passivation structure,

wherein the edge termination region is ohmically connected to the contact metallization layer.

18. The semiconductor device of claim 17, wherein a lateral distance between the inorganic passivation structure and the edge of the semiconductor substrate is smaller than a lateral distance between the edge termination region and the edge of the semiconductor substrate.

19. The semiconductor device of claim 1, further comprising:

a bond wire or solder structure in contact with the contact metallization layer.

20. The semiconductor device of claim 1, wherein the semiconductor substrate is a wide band-gap material semiconductor substrate.

21. The semiconductor device of claim 1, further comprising:

an electrical structure formed at the semiconductor substrate and having a breakdown voltage at least 100V.

22. The semiconductor device of claim 1, wherein the organic passivation layer continuously covers the inorganic passivation layer and at least parts of the contact metallization layer.

23. The semiconductor device of claim 1, further comprising:

an intermediate oxide layer,

wherein a first part of the intermediate oxide layer is arranged vertically between the contact metallization layer and the semiconductor substrate,

wherein a second part of the intermediate oxide layer is arranged vertically between the inorganic passivation structure and the semiconductor substrate,

wherein the intermediate oxide layer extends at least from the first part of the intermediate oxide layer to the second part of the intermediate oxide layer.

24. The semiconductor device of claim 23, wherein the inorganic passivation structure comprises a nitride layer, and wherein the first part of the organic passivation layer is located vertically closer to the intermediate oxide layer than the second part of the organic passivation layer.

25. The semiconductor device of claim 23, wherein the inorganic passivation structure comprises a silicon oxide layer and a silicon nitride layer, and wherein the silicon oxide layer is arranged vertically between the silicon nitride layer and the intermediate oxide layer.

26. A semiconductor device, comprising:

a barrier layer comprising a titanium sublayer and a titanium aluminum alloy sublayer; and

a contact metallization layer comprising aluminum,

wherein at least a part of the barrier layer is located between the contact metallization layer and a semiconductor substrate of the semiconductor device,

wherein at least a part of the titanium aluminum alloy sublayer is in contact with the titanium sublayer and the contact metallization layer.

27. A method for forming a semiconductor device, the method comprising:

forming a barrier layer comprising a titanium sublayer and a titanium aluminum alloy sublayer; and

forming a contact metallization layer comprising aluminum,

wherein at least a part of the barrier layer is located between the contact metallization layer and a semiconductor substrate of the semiconductor device,

wherein at least a part of the titanium aluminum alloy sublayer is in contact with the titanium sublayer and the contact metallization layer.

28. The method of claim 27, further comprising:

forming an inorganic passivation structure before forming the contact metallization layer.